New Design Tools and Processes Improve Customized ASICs.
By Donald Hawk and Kevin Kolwicz
The potential of 90 nm application-specific integrated circuit (ASIC) designs is introducing new packaging challenges that threaten the IC designer's ability to take full advantage of this advanced process technology. While the industry's primary focus has been on shrinking the size of silicon features, packaging considerations often have been more of an afterthought. There have been few innovations in packaging technology that can keep pace with the demands of Moore's Law.
In previous technology generations, packaging focused on the means to reduce bond pad pitch spacing around the periphery of the design. These efforts have led to staggered bond pad arrangements with effective pitches as small as 35 µm. Overall design and testing methodologies have not changed much; substrate routing, testing and verification is still done manually. Additionally, packaging often is not considered until after silicon design is complete. The size of the package design team is growing incrementally, as is package design time and the risk of error. Errors often remain undiscovered until prototype and may require both silicon as well as packaging redesign. This can delay a chip's time to market, as well as overall design cost.
null
Prior to 90 nm technology, flip chip packaging was an option for a select set of devices requiring high input/output (I/O) (>800) or high power (> 5 W). With the introduction of 90 nm ASIC technology, the gate densities, higher operating speeds, higher bandwidth serializer-deserializer (SerDes) requirements and higher power requirements will make flip chip packaging the technology of choice for the majority of devices. Additionally, the process of integrating previously separate devices and intellectual property (IP) into one device is proliferating the number (1,000 to 2,000) (Figures 1, 2) and types of I/O that are needed, including peripheral component interconnect (PCI), universal serial bus (USB), FireWire, small computer systems interface (SCSI), low-voltage differential signal (LVDS), stub series terminated logic (SSTL), and high-speed transceiver logic (HSTL).
 Figure 2. Patterns drive the place and route tools to exactly match this placement. |
null
While an area-array flip chip is the most efficient way to achieve the requirements described above for next-generation systems, it also is the most intrusive into the ASIC design process, requiring a new level of interaction between the silicon and packaging design.
Area-array flip chip design is capable of situating the signal bump location and associated I/O driver anywhere on the die's surface. The flexibility in placement of the I/O driver (Figure 3) and bump in the core region can reduce the overall die size when compared to stacking all the I/O drivers along the periphery. Performance gains also can be achieved by the closer placement of the I/O driver to the associated logic, thereby reducing on-chip routing distances and associated parasitics.
 Figure 3. I/O drivers are placed on a secondary placement grid by the co-design tool to match exactly the power grid structure in the design. |
null
Because of increasing complexity and interdependencies, a new design process must be introduced that integrates the knowledge and data of silicon, package and ASIC library designers, as well as that of computer-aided design (CAD) tool developers to enable concurrent package and silicon design. Packaging can be revisited quickly and efficiently at each stage of the process — from prototyping of the IC and package to determine pin assignment and routing to creating electrical models and to identifying package- and board-level problems.
Tools and methodologies have been developed that enable data sharing between teams to ensure final design accuracy, as well as to automate the packaging design process. Working out these issues throughout the design process ensures that a design is manufacturable, enables better chip performance, improves time-to-market and can reduce final design cost.
Facing the Challenges
The issues facing designers can be broken down into four interrelated challenges: cost, performance, signal integrity and time-to-market.
Cost. In the past, the package often represented a small fraction of total IC cost. However, the multiple routing layers and integrated thermal solutions required to handle today's 90 nm designs have put packaging costs on par with if not greater than the silicon itself. If not done properly, an IC's design can dictate an even more expensive packaging solution, such as additional routing layers or finer design rules. Therefore, package design cannot be done as an afterthought to the IC design process. This subtle change in the relationship between silicon and packaging costs has key ramifications. For one, the traditional approach of die-up driven design flow is no longer practical. And with the complexity of the silicon, neither is a packaging-down approach.
Additionally, the cost of making a mistake in silicon design or the substrate design has grown as mask costs and tooling charges have increased dramatically in the move to 90 nm mask sets and flip chip substrates. The interrelationship between silicon and packaging must be addressed from the beginning.
Performance. Area-array flip chip design involves placing I/O within the core of the IC, a process that can affect timing, routing density, signal integrity and overall design partitioning. With 130 and 90 nm technology, as well as 1.2 and 1 V operating voltages, even small voltage drops across the chip's power distribution system can result in unacceptable performance degradation. Flip chip packaging provides a natural means of delivering the power to where it is needed on a design. However, this also means the power grid structure of the IC and the package are tied together and must be considered as one in any analysis. A corresponding need is to dissipate more heat out of the package. The integrated ring and plate available with flip chip designs provide a natural heat conduction path to the environment or to potential packaging add-ons such as heat sinks.
Signal Integrity. With faster processors and higher bandwidth communications networks, there has been a corresponding jump in I/O speed requirements, stressing further the elements of packaging design. On a routine basis, OEMs are now integrating 2.5/3.125 Gbit/s SerDes subcircuit technology. These functional elements must be routed in the package substrate with impedance, skew budget and isolation in mind. Their relative solder bump positions and placement on the IC directly impact what can be achieved in successfully routing signals in the package and, ultimately, at the larger system level. Similarly, the integration of high-speed drivers depend on differential routing such as LVDS and current mode logic (CML) HSTL and SSTL drivers, which depend on multiple stable voltage supplies, require similar care for these signals to minimize noise on power and ground planes. The redistribution layer from the driver to the bump location also must be incorporated into the IC layout's parasitic extraction. While these considerations have played a role in past package designs, the sheer number of issues that future designers will face with 90 nm technology and the tight routing densities required are driving today's innovations in packaging design software.
Time-to-market. In this competitive world market that has dictated a move toward the foundry business model, there is a need to differentiate from the competition. One way to accomplish this is to get the design done right and on time the first time. This can be achieved only through an efficient design process and collection of feature-rich and fully debugged intellectual property. One part of the superior design process is the IC package co-design phase. New electronic design automation (EDA) tools coming online will provide new integration and capacity levels to handle these complex problems.
The product these EDA tools can build is only as good as its building blocks. Examples of such building blocks are the libraries of high-speed I/O drivers and SerDes macro blocks. These libraries need to be optimized for use in area-array flip chip designs. Finally, increased productivity is needed from both the IC and package design teams if they hope to handle this increased complexity in the face of a typical ASIC schedule striving to cut time-to-market.
Packaging and IC Flip Chip Co-design
The goal of the IC package/flip chip co-design process is to integrate the IC floor planning process seamlessly with the package substrate design process. Surprisingly, the link between the IC design process and package substrate design often has been through intermediate files (text files or unintelligent CAD data) because neither toolset was capable of reading the other's database. The latest co-design tools can read both IC and packaging databases. This permits design changes to be transmitted in both directions through the tools. Additionally, it speeds the design process as it reduces the chance for errors.
null
The new EDA tools with a co-design approach provide a view into both worlds. Rather than die-up or package-down, the co-design is based on a middle-out approach, where considerations from both IC floor planning and package design are factored into the design with the best chance to succeed. The targeted user of such tools is the IC designer or layout engineer because it primarily is the IC designer who has sufficient insights into the IC design in terms of placement, timing and signal integrity for today's designs. As a result, package design (substrate routing) must become a more automated process within the IC design tools. This permits the IC designer to evaluate multiple “what if” scenarios and achieve performance and cost targets before the design is sent to package design for completion.
How does one handle the complexity of such high I/O flip chip designs? An arbitrary placement of signals and power and ground cannot be routed in a substrate design. However, it is undesirable to constrain the bump pattern totally to ensure the package routing because of the mix of I/O and performance needs on the IC.
One way to handle complexity is by using patterns. This is seen in the use of object-oriented programming and hierarchical layout of IC designs. A pattern is made up of a set of bump placements and corresponding pieces of the IC design, such as driver placement and power busing, as well as aspects of the package design, such as the partial routing, vias and power planes of the substrate.
These patterns are available to the tools as library elements, which often are referred to as tiles, and incorporate the signals as well as proper ratios of power and grounds to meet performance requirements. The tiles themselves represent a degree of abstraction to what is being placed in the IC layout and package. As abstraction layers, they are easier to work with than moving individual drivers, wires and vias. Signals from the net list can be assigned to individual tile patterns of the appropriate type, such as LVDS and HSTL, and then placed relative to other aspects of the IC floor plan.
Once tile placement is complete, the abstraction can be removed and turned into the corresponding features written into the IC floor planning or database of the place and route tools. Matching elements also are generated for the package routing study. Depending on the tool, routability of the design can be evaluated within the tool itself or written into the appropriate database format of package design tools.
Area-array Flip Chip Co-design
The complexity and planning of area-array flip chip designs highlight the value of the co-design approach. EDA tool integration with the IC package design process leads to an optimization level that is carried through into the design of the I/O libraries.
The co-design concept is crucial to efficient and timely ASIC product development using the tight geometries and innovative packaging options associated with next-generation semiconductors (Figures 3, 4). Co-design also can have benefits and payback when used with more traditional products.
DONALD HAWK, consulting member of technical staff, and KEVIN KOLWICZ, director, technology strategy, may be contacted at Agere Systems Inc., 1110 American Parkway NE, Allentown, PA 18109; phone: (800) 372-2447; e-mail: [email protected], [email protected].