September 9, 2003 – IBM says it has developed two new chip manufacturing technologies that could improve CMOS performance by more than 60%.

Combining two silicon substrates in the same wafer increases the mobility of positive charges through device channels, resulting in performance improvements of 40%-65%.

IBM has also reportedly found a way to make strained silicon directly on insulator bypass the silicon on germanium layer, which could yield 20% to 30% performance improvement at volume production levels.