Silecs pursues a non-porous low-k solution

Start-up Silecs has entered the low-k fray with an organosiloxane-based low-k dielectric material that is effectively non-porous. The company was founded in 2000, is supported by organizations funded by the government of Finland, and has access to the semiconductor processing facilities at VTT Microelectronics Laboratories.

While the ongoing industry battle has been between CVD and SOD processes used to make low-k dielectrics, Silecs straddles both worlds. The company’s materials are developed using the SOD process, however, “since [the materials] integration behavior has been shown to be similar to that of TEOS, they are expected to facilitate the adoption of ULK dielectrics into standard IC manufacturing processes,” explained Bob Donia, VP of business development at Silecs.

Key to the technology is a three-component precursor system comprising functional groups, bridging groups, and cross-linkers. “The material is constructed using a modular approach that enables tuning of the dielectric constant between 2.2 to 3.0 without specifically adding pores,” says Donia.

The modular approach could work like this: The organic functional group might be selected to optimize a specific property (e.g., tune polarizabilities, stabilize dipolarities/charges, allow photosensitivity), while the bridging group would be selected to optimize another capability (e.g., thermal/mechanical stability, CTE adjustment). The cross-linking group would be selected for yet another property (e.g., thermal/mechanical stability, eliminating pore formation). The idea is to get the best balance of properties.

While the materials are effectively non-porous, the total porosity is actually 8% to 12% with an average pore size less than or equal to 1.0nm. The glass transition temperature is greater than 450°C — high enough to go through substrate processes without melting or changing properties.

Many of the precursors used in the process can be photosensitized. “A photosensitive dielectric allows for direct patterning of the dielectric, eliminating several lithographic steps,” notes Donia.

The company’s first alpha testing partner, Cypress Semiconductor, just completed its evaluation. A second alpha test partner — an unnamed IC manufacturer in Europe — has also agreed to work with Silecs. Meanwhile, the company expects to have a production-proven process ready by the end of 1Q04. — Debra Vogler, Senior Technical Editor


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