Solder Ball Endurance

Understanding material and process effects

By Terence Collier

Ball shear strength alone does not guarantee a reliable package. By design, ball grid array (BGA) and chip scale package (CSP) device families have to overcome repeat temperature extremes and environmental conditions.

The three most common root causes leading to package and device failure are inadequate qualification, solder voiding (usually due to poor processes), and an incomplete understanding of material properties that can lead to intermetallic compound (IMC) formation, fatigue and finally failure.


To determine the robustness of a process, device and package, qualification procedures have been established and documented per JEDEC (and mil-spec) requirements. As templates, with some manufacturers adding additional restrictions to further guarantee reliability and performance, these plans are executed and the results summarized to determine if a product is acceptable for release. JEDEC also allows suppliers to use qualification by similarity (QBS) when the target parameter(s) are fully understood and data exist to warrant omitting a specific test.

Going forward with lead-free solutions and smaller CSPs, temperature cycling (TC) and thermal shock (TS) (or any of the other qualification tests that subject packages to elevated temperature) offer an opportunity to discuss the merits of QBS. QBS can be abused to reduce qualification time when TS is used in lieu of both TS and TC to qualify traditional integrated circuits (IC) in tin/lead (Pb/Sn) assemblies. (For this article, Au is used as an example to study the effects of time and temperature on package robustness and reliability.) TC subjects the assembly to a cyclic temperature from -65° to 150°C per JEDEC for 100 to 1,000 cycles. TC similarly subjects a package to temperature cycling between -65° to 150°C. The difference is the dwell time (higher for TC) and the ramp (steeper slope for TS).

The key factors for intermetallic growth are material (Sn, Au, Pb, etc.) availability and both the temperature and time component of the thermal curve. The growth of gold IMCs primarily is a function of the cumulative time amassed near 150°C during TC since gold IMCs begin to grow above 125°C via solid solubility (Figure 1). TS better evaluates thermal-mechanical effects, such as mismatches in coefficient of thermal expansion (CTE), so the two types of test are not 100 percent interchangeable. TC customarily will reveal a shorter expected life (as reflected in a Weibull plot) than TS.

Figure 1. An intermetallic layer has grown to a thickness comparable to the copper thickness after fewer than eight hours at 150°C.
Click here to enlarge image


A study of BGA burn-in sockets with Au contacts confirms the growth of IMCs at the ball/socket interface. Roughly

10 percent of the contacts were contaminated with solder material in addition to suffering damage after only nine hours at 125°C, and 100 percent of the contacts were contaminated with all of the balls damaged after 24 hours at 150°C. Similarly, other work confirms that TC is a better vehicle for evaluating IMC formation, failure modes and robustness than TS. As discussed earlier, the work confirms that dwell time of TC subjects assemblies to more severe stress testing than TS. Simulating user practices and incorporating them into the qualification plan, specifically for lead-free, provides additional insight as well.

Qualification plans that mimic end user flows also have been incorporated and do indeed help to predict reliability. Repeated baking, multiple reflows and high-temperature storage all impart thermal energy necessary to exacerbate IMC formation. Baking is required for packages with poor moisture sensitivity level (MSL) performance. Lead-free material sets tend to have inferior MSL performance and require higher processing temperature, so they may be subject to increased damage.

QBS has merits, but prior to implementation, the proposed omitted steps should be evaluated. For example, if a CSP/BGA ball or bump has a dimension D, then the area (ball contact to pad) is proportional to D2 while the volume is proportional to D3 (A=πD2 and V=1/6πD3). Changing ball size from 0.3 to 0.6 mm (including a ±0.05 mm tolerance) can produce a 7X change in area at the bond interface, which can change the shear strength significantly. This change in ball size results in a change in solder ball volume and mass of almost 18X.

Solder Voiding

Inevitably, there are failures during qualification and reliability testing. When performing root cause analysis of CSP/BGA failures, it is not unusual to find voids in solder joints. Although voids themselves may not be the direct cause of the failure, voids may provide nucleation sites for defects that lead to catastrophic failure.

Knowing the damaging effects of voids on long-term reliability, it is unfortunate that there are no standard specifications that provide pre-inspection criteria to screen potentially damaging voids. The supplier typically has the burden of performing detailed analysis to determine how, when and if a void could jeopardize long-term reliability. There are numerous factors to consider when establishing void criteria.

Figure 2. Schematic drawings showing an acceptable solder ball (upper left) and various configurations containing voids.
Click here to enlarge image


Size, location and void frequency should be considered when determining a solder joint's robustness and reliability (Figure 2). Generally, poor process control or inadequate solder material selection can be identified as the cause of voiding in solder joints. Experience has shown that neither the supplier nor the user is immune from poor process control.

Size. Perhaps the most critical, the size of the void can negatively impact the solder joint by becoming a source for contaminant entrapment, a stress riser, a thermal barrier and electrical degradation by restricting the path of current flow. Depending on the size of the void, the effective life of a component could be reduced by 50 percent or more.

If other process control factors are marginal, such as those that contribute to ball deformation, the problem is further compounded.

Larger voids typically decrease the robustness of the solder joint compared to small voids because the likelihood for failure increases dramatically as the solder material thickness between the void and the ball exterior decreases. For example, a 0.007″ ball with a 50 percent void has approximately 0.0017″ on each side of the void, while a 0.004″ ball with a 50 percent void has only 0.001″ on each side. The void's impact becomes more severe if it is near one of the bonding interfaces.

Location. Void size and shape are important, but equally important is void location. While voids in the main solder joint may be less severe, reduced cross sectional areas near bonding interfaces can adversely affect short-term as well as long-term reliability. With a reduction in cross sectional area, specifically when voids are located at the ball/interface attach site, current flow is restricted, shear strength is reduced proportionally to the decrease in bonded material and the solder joint stability will degrade more rapidly with increased temperature cycling. Specifically, voids near interfaces with the greatest CTE will degrade and fail in the shortest time.

Frequency. CTE mismatch effects may be further compounded by many small voids. A conglomeration of many small voids, each with a distinct localized stress gradient, provide a path for crack nucleation and growth. Combined with a high-stress concentrator, such as CTE mismatch, fatigue and failure could occur in the adjacent structure as well as the solder.

Unfortunately, smaller voids may be more difficult to detect than larger voids during process inspection. X-ray tools may have to be tuned or positioned at off angles to resolve the small features. Additionally, because small voids may be less buoyant in the bulk solder, they may be more difficult to remove. Stating the obvious, process control must be optimized to prevent the formation of many small voids.

Voids, regardless of size, also may exacerbate IMC formation and the aftermath. As previously mentioned, voids will increase the overall stress level of the solder joint and reduce the volume of alloying materials available for reliable solder joints. Consuming barrier material (gold), additional IMCs could form, further reducing the assembly's life.

Intermetallic Formation

Because of solid solubility, Au/Sn IMCs can grow at moderate temperatures (~125°C) even though the solder may never become molten. The growth hastens at moderately higher temperatures (~150°C). Packages may be repeatedly subjected to extended temperature extremes at burn-in, MSL baking, storage, test and during SMT reflow. Interfacial cracks, balls falling off the package (pre- and post-reflow), reduced ball shear, and parametric and functional shifts in device performance commonly top the pareto list of problems resulting from intermetallic formation. Some lead-free alloys may provide relief to Au/Sn intermetallic effects, although the lead-free alloys may introduce other concerns.

The silver constituent in Sn/Ag/Cu lead-free solders can help prevent the dissolution of gold into solder joints. Gold is used as a barrier layer in lead finishes, multilayered laminates (CSP/BGA) and PCBs. However, when in contact with Sn or Pb, Au can lead to the formation of detrimental IMCs. IMC formation can lead to shifts in circuit functionality, reduce the bond strength of solder joints and contribute to cracks. Gold/gold IMCs also migrate away from the barrier interface exposing underlying metals to conditions favoring additional IMC growth, inhomogeneous areas, alloy separation and nucleation sites for cracks.

Evaluation of the current material sets should help determine the performance at lead-free reflow temperatures (260°C). Regardless of package type, the two most common deficiencies have been increased IMC growth and reduced MSL performance. On average, the MSL dropped by two levels of sensitivity with CSPs, modules and small profile TQFPs.


Consider the following real example. To reduce the bake time prior to bagging and shipping, a process improvement team pushed the 150°C envelope. The original process specified 125°C for 24 hours. MSL labels were attached to the bag exterior authorizing a 150°C four-hour bake to prevent moisture-induced reflow damage. After numerous complaints and the return of a few hundred thousand units, the problem was noted, diagnosed and corrected.

This and many other examples indicate inadequate understanding of properties that will affect device reliability. To move forward with lead-free materials, the lessons learned working with traditional Sn/Pb solders may have to be painstakingly relearned.


For a complete set of references, please contact the author.

TERENCE COLLIER may be contacted at TQC Solutions USA, P.O. Box 2504, Rowlett, TX 75088; (214) 557-1568; E-mail: [email protected].


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.