Getting a handle on the reliability of devices using new low-k materials and copper interconnects is key to successful integration efforts. Traditional reliability models are not able to predict breakdown in thin oxides or the impact of voltage and temperature stresses on the dielectric constant of materials. Recently, Applied Materials announced it has developed benchmarks for testing the electrical reliability of copper and low-k materials using Agilent Technologies’ Parallel Parametric Reliability (PPR) test system.
“Breakdown [in thin oxides] is not detectable by traditional reliability systems because it does not behave as predicted by the traditional models,” explains Louis Solis, project manager at Agilent for the overall test system called Tesla, of which PPR is the solution for predicting long-term reliability.
Specifically, Solis notes that it is for oxides greater than 4nm that the model for time-dependent dielectric breakdown (TDDB) of oxide is well understood. But for oxides less than 4nm, soft breakdown, (i.e., the breakdown does not occur at a well-defined point in time or at a specific current value) is not well understood.
Additionally, self-annealing effects in PMOS devices muddy the waters (negative bias temperature instability, or NBTI). “When a negative bias is taken away from the gate of a PMOS device, some of the holes [that had been trapped in the gate oxide] de-trap and the device ‘recovers,’ continues Solis. But these apparent recoveries can fool test-measuring instruments that are not fast enough to measure transistor characteristics once the negative bias is removed before this so-called relaxation effect has occurred, or if the time between measurement and stress is too long.
Other issues in traditional reliability measurement tools are that small variations in stress voltage also affect the device breakdown, according to Solis. Examples include the inability of providing ramp vs. step-stress — which can damage low-k materials. Algorithms used by the Tesla system enable selection of test and detection conditions.
Furthermore, to measure the impact of voltage and temperature stress on the dielectric constant of high-k and ULK dielectrics, capacitance measurements are made by the PPR system.
Besides reliability issues with new materials at the 90nm and 65nm nodes, saving time and money on unnecessary steps are also important considerations. By testing devices on the wafer, spatial correlation — the location of a weak die on a wafer — is preserved, thereby easing root cause analysis of early failures. “Depending upon the process, there may be a failure pattern,” explains Solis. “For example, a wafer may have center-to-edge variation in TDDB indicating a variation in process, rather than an inherent gate oxide problem.” — Debra Vogler, Senior Technical Editor