IMEC, EV Group team to work on wafer-level packaging

The team intends to tackle roadblocks in the further downscaling of IMEC’s thin-film multilayer technology below 5-micron-wide line and space interconnects. They also plan to develop 0-level packaging techniques for MEMS devices, aimed at achieving simple and cheap polymer bonding processes on 200-mm wafers.

(October 30, 2004) San Jose, Calif.&#8212The Semiconductor Industry Association (SIA), in a newly released study of China’s emerging semiconductor industry, calls for changes in the country’s “discriminatory value-added tax (VAT).” SIA reports that the VAT is a rebate scheme distorting trade investments and imposing cost penalties for semiconductor importers trying to compete for sales in China.


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