Amkor’s power SiP addresses thermal challenges

(February 3, 2004) Chandler, Ariz.&#8212Amkor Technology Inc. is using its system-in-package (SiP) technology to solve the challenges of thermally demanding DC/DC power-conversion applications.

The first implementation of this expanded capability integrates components for a 15-amp DC/DC point-of-load converter into a land grid array (LGA) package for Power-One, Inc., based in Camarillo, Calif. Amkor’s LGA “Power SiP” is the platform for Power-One’s X3015P, which is the first product in the company’s new maXyz family of DC/DC converters. The X3015P is the industry’s first semiconductor-like POL converter of this type approved by Underwriters Lab in the U.S. and TUV Rhineland in Europe.

Flip chip epoxy fluxes from Indium

(January 28, 2004) Utica, N.Y.&#8212Indium Corp. has rolled out two flip chip epoxy fluxes, PK-001 and PK-002, designed for use with Sn 62 and Sn 63 eutectic solders.
PK-001 and PK-002 are fast curing, halide-free, no-clean fluxes that are suitable for flip chip or chip scale package soldering processes.

The environmentally friendly fluxes have a stable thermoset residue that is compatible with standard underfill materials, conformal coatings, and most other coatings and finishes. Pin transfer, stencil printing, dispensing or dipping techniques can be used to apply the fluxes.

Toshiba develops 9-layer MCP

(January 23, 2004) Irvine, Calif.&#8212Toshiba Corp. has developed a multichip package (MCP) of 1.4-mm thickness that can stack 9 layers (6 memory chips with 3 spacers).

Toshiba used advanced process and mounting technology to shrink each memory chip to 70-micron thickness, and then bond the chips together in one package by wires. The miniature MCP consists of a combination of memory chips, such as SRAM, SDRAM, NOR flash memory and NAND flash memory, and has a total capacity of 776 megabits (Mb) in one sample application. Toshiba plans to launch new MCP products in May 2004.

Altera unveils two new FPGAs

(January 20, 2004) San Jose, Calif.&#8212Altera Corp. has introduced two industrial-grade members of its Stratix family of fine-pitch ball grid arrays (FPGAs), the EP1S80 and EP1S60.

The EP1S80 device provides more than 79,000 logic elements and over 7Mbits of internal memory, making it one of the largest 0.13-micron industrial-grade FPGAs available.

Wells-CTI introduces 0.5-mm CSP socket

(January 19, 2004) Phoenix, Ariz.&#8212 WELLS-CTI, a supplier of burn-in sockets, has a new socket line designed to reduce the total cost of test.

The 718M Series clamshell CSP accommodates up to 4 devices and is a 0.5-mm CSP multi-site socket offering.
The socket’s floating plate and pressure pads enable the multi-site design. Its floating plate allows each device to be positioned properly, with precision alignment, by suspending the device over the socket’s contacts. As a result, devices interconnect only when the pressure pads are applied when closing the clamshell lid. Once the lid is closed, the independent pressure pads allow for individual intimate interface with each device. This also allows for individualized pressure application, as the force applied to each device is not dependent on the overall thickness of the other devices.

Agilent rolls out RF SOC test solution

(January 13, 2004) Palo Alto, Calif.&#8212Agilent Technologies Inc. recently rolled out a new low-cost RF SOC test solution that tests, in quad-site, all devices in a wireless radio for all wireless applications for less than $860,000, comparable to industry expectations.

The solution includes a new RFIC IQ analog option, which provides the performance demanded by the high data rates of emerging wireless standards, including 3G and 4G.

Kulicke & Soffa introduces ultra-high-speed ball bonder

(January 12, 2004) Willow Grove, Penn.&#8212Kulicke & Soffa Industries, Inc. (K&S) has introduced the Max&#181mplusT Ultra High Speed Ball Bonder for all types of ultra-fine pitch applications, including 35-&#181m in-line pitch. Based on the technology of K&S’ Maxum IC Ball Bonder, the Maxµmplus delivers bond placement accuracy of 2.5 &3181m, at speeds up to 10 percent faster than the Maxum.

An improved servo control system for the X-Y Table reduces wire cycle times to 63.0 msecs. Performance is maintained for the largest bonding area available in the market &#8212 56 mm (2.20″) x 66 mm (2.60″). Precision-touchT bondhead technology delivers optimum bond force control. Advanced teaching and calibration software improves overall accuracy to 2.5 &#181m. The Max&#181mplus also incorporates a reduced-friction wire feed path with the capability to handle wires down to 15-&#181m diameter.

STATS unveils ‘green’ flip chip land grid array package

(January 6, 2004) Singapore&#8212 ST Assembly Test Services Ltd. (STATS), an independent semiconductor test and advanced packaging service provider, has qualified a new environmentally friendly version of its Flip Chip Land Grid Array (FCLGA) package.

The lead-free FCLGA is targeted at high frequency and/or high data rate applications such as mobile phones, WLAN modules, PDAs, digital cameras and camcorders, which are driving low-profile, high-performance, environmentally friendly packaging options. As with all of its flip chip package offerings, STATS provides full turnkey support, including advanced design and simulation support, wafer bumping, wafer probing as well as assembly and test.

Pump technology from Speedline

(December 31, 2003) Franklin, Mass.&#8212Speedline Technologies’ MPM’s next-generation pump technology is designed to reduce materials costs, facilitate quick changeovers, and expands the range of usable materials. The system represents a unique approach to paste management, featuring a smaller paste chamber that reduces materials waste and compaction, and disposable inserts for simplified cleaning and reduced maintenance downtime. The pump uses standard paste cartridges and the company’s patent-pending printing technology to deliver quality print results. It also includes a disposable, quick-change blade system, and is compatible with the company’s MPM AP Excel platforms.

Datacon improves its 2200 apm multi-chip die bonder

(December 22, 2003) Trevose, Penn.&#8212Datacon North America, Inc. has improved its 2200 apm Multi-Chip Die Bonder platform. The Datacon 2200 apm+ Multi-Chip Die Bonder takes the Datacon 2200 platform concept to the next level, handling wafers up to 300 mm and die up to 50 mm, according to the company, in addition to handling specialized advanced packaging needs.

Recent testing performed on 2200 apm+ machines revealed performance better than published specifications. Overall machine accuracy on machines shipped to customers increased to 7µm@3s, in addition to actual production throughput increasing by 25 percent. Throughput ranged from 1000 UPH for high-end singulated flip chip applications (incl. flux dipping) to 3000 UPH for low-end matrix flip chip applications (excl. flux dipping).

Lead-free, no-clean solder paste from Northrop Grumman’s Kester Grumman

(December 17, 2003) Des Plaines, Ill. &#8212 Northrop Grumman Corp.’s business unit Kester has introduced a new lead-free, no-clean solder paste. Kester’s R905 is engineered specifically for the extreme thermal demands of assembling with higher melting temperature lead-free alloys such as the Sn/Ag/Cu (SAC) family.

R905 is formulated for consistent release from the stencil for critical fine-pitched applications (0.4mm/16 mils) with anti-slump characteristics and preferred solder deposit definition.

JPSA introduces tabletop beam delivery system

(December 15, 2003) Hollis, N.H. &#8212 JPSA Laser’s Microtech modular tabletop Beam Delivery (MBD) system is a low cost, compact, full-featured UV laser beam delivery and microscope camera system designed for materials processing research.

The system is a flexible beam delivery platform designed to mount on a standard optical breadboard, a portable tool for applications such as lithography, selective material removal, 3-D micromachining, high-precision drilling, cutting, marking and surface scanning.

Helic unveils EDA tool

(December 12, 2003) Athens, Greece&#8212Helic S.A. has rolled out VeloceRF, an EDA tool designed to enhance popular industry design environments to enable delivery of first pass RF ICs and systems-in-package, significantly shortening the development cycle for complex wireless transceiver products.

The system constitutes a major step forward in true RF IP portability and design reuse; by enabling rapid and accurate inductor modeling &#8212 including mutual inductance &#8212 as well as inductor synthesis inside the flow, it supports whole-chip modeling of RF ICs without reliance on pre-characterized inductor models. VeloceRF-generated models of RF IP blocks are available throughout the design flow, providing designers with netlists fully-loaded with electromagnetic effects and parasitics and enabling them to rapidly customize and optimize RF performance.

BP Microsystems introduces automated programming system
(December 10, 2003) Houston, Texas&#8212BP Micro’s new 3600 is ideal for production environments where speed and flexibility are critical, according to the company. The new system’s technology programs near the theoretical limits of the device while closely following the semiconductor manufacturer’s specifications.
Toshiba offers lead-free ahead of schedule

(December 8, 2003) Irvine, Calif. &#8212 Delivering on its plan to provide environmentally friendly products by using lead(Pb)-free packaging, Toshiba America Electronic Components, Inc. has announced that many of its extensive line of power semiconductor package types will be manufactured using either lead(Pb)-free packaging or lead(Pb)-free finishes.

Developed by Toshiba Corp., the diverse line of power devices feature high-power IGBT modules and press packs, plus a comprehensive line of medium-power devices that include MOSFETs, bipolar transistors, Schottky Barrier diodes, intelligent power modules, thyristors and triacs, and rectifiers. The high-power devices are optimized for industrial control applications, while the medium-power devices are targeted for use in portable applications where small size and performance are important factors.

Sez Group unveils ‘Galileo’

(December 4, 2003) Chiba, Japan&#8212The SEZ Group, an innovator in single-wafer wet-processing technology for the semiconductor industry, today announced it is expanding its portfolio of substrate-etch tools with a new system designed to address the growing demand for thinner, higher-performing IC packages.

The new Galileo(TM) system, dubbed the GL-210, leverages SEZ’s proven wet Spin-Processing technology in a single-wafer system that delivers superior wafer thinning, surface conditioning and stress relief for two key new sectors &#8212 back-end assembly/packaging, and front-end wafer manufacturing.

Dow Corning Electronics rolls out low-stress patternable materials

(December 3, 2003) Midland, Mich. &#8212 At Semicon Japan, Dow Corning Electronics today introduced two new product families of low stress, patternable, silicon-based products. The WL-3000 and WL-5000 series of products are low-modulus, low-cure-temperature materials designed to enable the production of highly reliable packages processed at the wafer level. These new product lines aim to safeguard the performance and yields of packaged microelectronic devices, while giving users a choice in the patterning process.


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