Op-amp Performance

This article looks at the effect that different mold compounds have on assembly-induced package shift for different types of op-amps.

By Marty Grabham and Lance Clinton

To understand the impact of package stress, what key parameter of an operational amplifier (op-amp) the stress affects most must be considered. A general-purpose op-amp specifies an input offset voltage (VIO). This parameter is the DC voltage that must be applied to the input terminals to cancel the DC offset within the op-amp to force the quiescent DC output voltage to a specified level (Figure 1). This offset mismatch in the input stage (transistors and components) during silicon die fabrication creates effects that produce a mismatch of the bias currents that flow through the input stage, resulting in a differential voltage (Vd). This parameter itself determines the precision of a particular op-amp's performance. The smaller the VIO, the better the performance characteristics in a typical application. Most op-amps have an input-stage that is a precision-mirrored, two-sided design (Figure 2). This technique reduces the changes in the output voltage to ensure uniform changes due to stress levels. The input stages of most op-amps are cross-coupled in the design layout to minimize the effects of these stress gradients.

Figure 1. Input offset voltage test circuit.
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Because of this known VIO, several techniques have been implemented to offset for wafer process variation. If the input stage is perfectly symmetrical and the transistors perfectly match then VIO = 0. But due to process variations, geometry and doping are never exact; all op-amps require a small voltage between their inverting and non-inverting inputs to balance these mismatches. Most high-precision op-amps use either a zener or fused trimming procedure to “trim in” the VIO due to process variance. These components are tied to a bank of resistors that vary in size based on the amount of trim necessary to dial in this VIO parameter. The major disadvantage of adding trim components to a design is the increased die size, producing fewer chips per wafer. Also, a trimming procedure will only improve the device's performance in the pre-package stage. The designer must consider the mechanical stresses applied to the device during encapsulation. The data illustrated in the images indicates that a significant amount of package shift occurs following encapsulation.

Figure 2. Input stage.
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Careful planning with the design layout will improve VIO performance with respect to package shift (Figure 3). A key performance aspect of differential amps is the minimum DC differential voltage that can be detected. The presence of mismatched components with the amplifier itself and drifts of its values with temperature produce differential voltages at the output. This output signal is unrecognizable from the amplified signal. Consideration of mismatch-induced offsets is centralized to the design of analog circuits. Two quantities represent the DC performance and the effect of mismatches: the VIO and current.

Figure 3. Stress gradients from a “package point of view.”
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Sources of offset error from a process point of view is in the emitter-coupled transistor pair at the mismatches in the base width, base-doping level and collector-doping level of the transistors, mismatches in the effective emitter area of the transistors, and mismatches in the collector load resistors.

Under stress, silicon exhibits resistivity changes. These variations in stress produce changes in resistor matching across the die. Some layout techniques have been developed to minimize resistor stress sensitivity. A linear design can vary from one to the next due to different forms of packaging material that produces different modulus (thermal) characteristics. The thermal expansion of plastic encapsulation is approximately 10 times that of silicon. As this encapsulated package cools, it shows a difference between the coefficients of thermal expansion (CTE) of silicon. This causes the epoxy to remain frozen in the packaged device, forming residual stresses (Figure 4). VIO measurements during pre- and post-packaging reveal differences referred to package shifts, which are proportional to the amount of residual stress. Package-shift lowers the device's VIO precision and causes test yield issues. By careful planning and layout of a linear design, the sensitivity of the circuit can reduce these package shifts.

Figure 4. Stress distribution across a typical IC.
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Location- and orientation-matched devices should be placed where the die's stress gradients are smallest. The best location is the center of the die for matched components. Never place critical components near the corners, where the stress intensity and gradients reach the maximum values.

Die Coating

Several methods other than design/layout considerations exist for minimizing package stress. One of these methods is coating the wafer with a polyamide resin. This resin overcoat provides a mechanical compliance between the mold compound and the die. Device potting is another technique where a compound is applied to the silicon die following the die attach and bond assembly operation. This potting compound creates a cushioned barrier between the die silicon and the plastic encapsulation, greatly reducing the post-encapsulation VIO in precision op-amps. This technique is not widely used due to added assembly costs. Further development of this procedure for newer products is not feasible because of the complexity of smaller packages and because lead-frame designs limit available space between the top of the chip and the package. This item needs to be analyzed carefully. Otherwise, it can cause quality issues such as voids, pits and cracks in finished goods.

Mold Compound

Mold compound often is the primary cause behind device package shift issues. Mold compound experiments were performed to examine the effects of mechanical stress applied to op-amps during encapsulation. The experiment performed used multiple types of mold compounds, providing for a comparison between the different degrees of mechanical stress that each compound imposes on an op-amp device.

Experiment Procedures and Results

The first step in these experiments was to probe an op-amp device wafer to collect pre-packaged parameter readings, providing a comparison with post-package measurements. Multiple die were assembled from the wafer using three types of mold compounds (unless noted, all devices were assembled in eight-pin SOIC). Then these mold compounds were classified by stress grading (high, medium, low).

Finally, the packaged units were tested using automated test equipment to obtain post-package parameter values. For all mold compound experiments, the results showed that VIO is the only parameter that varies significantly due to package shift. Apart from gross functional and continuity failed units (most likely unrelated to package shift), only four units out of 2,700 (0.15 percent) failed for anything other than VIO. Because of this, VIO is the only parameter analyzed in terms of yield increase/decrease.

Pre-package analysis according to probe data showed that approximately 95 percent of VIO readings for the wafer used fell within the VIO specification range. The 95 percent VIO yield changes significantly after the application of mold compound during packaging.

Table 1 shows a summary of yield estimates according to mold compound/die coat. To calculate the percentages in the table, the mean and standard deviation was first calculated for each amp (dual-amp device) in each set of devices. A normal distribution curve then was created with this mean and standard deviation. The area defined by the device limits was used under the normal distribution curve to calculate the probability of passing for each amp. The overlapping area for each individual amplifiers curve (multiply Amp1 probability by Amp2 probability) resulted in the overall yield probability results.

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Figure 5 shows approximate normal distribution curves for the mold compound evaluation. This figure assumes an equal sample size for all conditions using the mean and standard deviation for each mold compound evaluation as the means to create the curves.

Figure 5. VIO distributions.
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The VIO distribution is spread out with respect to probe results during assembly/package. The lower/upper specification limit (LSL/USL) markers show the limits as defined by specification for a particular device (±800 µV). In comparison to these limits, spreading often causes significant yield loss for high-grade (low VIO) op-amp devices. It also is noticeable that the centers of the curves shift to the left from pre- to post-package. Data indicates that this shift may occur to the left, right or not at all. One constant is that the post-package VIO distribution has a higher standard deviation than pre-package form. Each mold compound creates a different distribution according to its stress properties.

High-stress material exhibits angular fillers, which is a characteristic of material that can cause additional stress. Low-stress material shows spherical fillers, characteristic of material that would cause fewer problems due to excess stress on input components. Generally, filler content is indicative of how low the CTE will be for a particular mold compound. Table 2 shows the filler content percentage for the low-, medium- and high-stress compounds.

To verify that package stress was the culprit of yield loss in this experiment, samples of units were de-capped (mold compound above die removed) after test. VIO readings were improved after de-cap, confirming that the mold compound packaging was indeed the culprit of the parametric shift.

The team tested additional devices pre-package vs. post-package during another experiment with one mold compound only in PDIP package types to show that a similar package shift exists with most common package types. The PDIP package showed similar results when it was compared to the SOIC devices.


Lower stress mold compounds are preferred with respect to device performance for higher-grade op-amps with tight VIO specification limits. These mold compounds decrease the distribution spread of VIO due to package shift and show no detrimental affects to other device parameters. Die coat also contributes to device yield, but to a lesser degree than a low-stress mold compound.

Design and layout techniques relating to package stress always should be considered when designing a high-grade op-amp. While package shift problems may never be eradicated completely, a well-thought-out design in conjunction with proper layout techniques can minimize many of the stress-related offset voltage shift problems encountered with op-amps.

For a complete list of references, contact the authors.

MARTY GRABHAM and LANCE CLINTON, linear products engineers, may be contacted at Texas Instruments, Dallas, TX; E-mail: [email protected].


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