A review of challenges for high-density applications as well as CSP design solutions.
By Jeffrey C. Demmin
Chip scale packaging (CSP) has been driven primarily by the small form factors required for portable electronics and other high-density semiconductor applications. It has been shown that reliability requirements can be met in spite of the design constraints imposed by these applications. Even when the form factor dictates a stacked approach, ultra-thin CSPs can be stacked and still meet — and exceed — the physical and reliability requirements.
This article reviews some of the challenges for high-density applications, as well as some of the CSP design solutions that are meeting them. For example, reliability tests such as drop and vibration are becoming more important for portable electronics, and this article discusses the results of µZ-Ball Stack*, one company's stacked CSP solution, in those and other tests.
Package Reliability in Portable Applications
It is no surprise to cell phone and PDA users that drop impact is a common cause of failure in portable electronics. Sophisticated equipment has been developed by the National University of Singapore, among others, to evaluate the drop test reliability of portable consumer electronics products. The set-up includes the ability to drop the product at specific angles, with high-speed cameras to verify and record the drop. Detailed modeling also has been used to assess the drop impact reliability of product designs, with sub-modeling techniques used to look at crack initiation in CSPs during the impact. This is required because much of the force of the impact is transmitted to the semiconductor packaging structures within the product.
One approach to improving board-level reliability of packages in cell phones is the use of an underfill material to attach the package body to the board. This adds processing steps, but it has been shown to increase the performance of certain types of CSPs in bending and shear tests. However, the rework process decreases the robustness in drop tests.
Chip manufacturers have developed extensive modeling approaches to develop packages that meet drop test and related requirements for portable applications. STMicroelectronics, for example, has developed and verified a life prediction model for board-level drop tests. The variables include component orientation, solder fillet, solder joint location and the material properties of the various components.
One packaging solution that addresses the design and reliability requirements is CSP stacking, with maximized density in the X-, Y- and Z-directions. One such structure is discussed below.
Stacked CSP Design
The µZ-Ball Stack package structure (Figure 1) is an extension of its established predecessor, the µBGA-W (wirebonded µBGA)**. Multiple µBGA-W packages are vertically interconnected through BGA solder balls to form a multichip CSP that fits within a footprint nearly equivalent to a single-chip CSP. Keeping a CSP footprint retains the performance and form factor advantages, making multichip CSPs appropriate for portable applications.
 Figure 1. An example of the µZ-Ball Stack package structure. |
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This package stacking approach also allows standard assembly and testing of individual components prior to stacking, which provides cost advantages because it avoids the compound yield issues associated with stacking bare chips that typically are not or minimally tested. It also allows burn-in without resorting to wafer-level or other bare-die burn-in technologies, which still are not a cost-effective production alternative.
Reliability Testing
Reliability testing has been performed on daisy-chain test vehicles of 2- and 4-die stacks of the µZ-Ball Stack. These tests include:
- Moisture sensitivity determination: JEDEC Level 2
- Unbiased autoclave: 121°C, 100 percent relative humidity, two atmospheres, 168 hours
- Board-level thermal cycling: air-air thermal shock chamber; -40°C/125°C 10-minute dwells, 10-second transfer times, 30-minute cycle times
- Board-level drop testing: 1,500 G acceleration.
- Board-level vibration testing: 20-2,000-20 Hz sweeps, four five-minute sweeps per axis.
Free-fall drop testing was performed on packages mounted onto test boards. The test boards were screw-mounted to drop table standoffs at six locations around their periphery to allow the center of the boards to flex freely during testing. Parts were oriented in a horizontal orientation. The drop table itself was guided using vertical rails to ensure repeatable shocks. The 1,500 G peak acceleration was established using a piezoresistive accelerometer mounted on the drop table. Dropping onto a 1.6 mm thick felt pad on concrete from a height of 0.6 m gave a 0.5 ms 1,500 G pulse on impact. Vibration testing consisted of a sine sweep from 20 to 2,000 Hz with peak acceleration of 20 G. Each test board was fastened to the vibration fixture at the board ends and along the transverse axis near the middle of the board.
Results for some of the completed tests are summarized in Tables 1 through 3. Figure 2 shows X-ray imaging of 2-die stacked CSPs, which was one tool used to evaluate the mechanical reliability of the test units. The results for thermal cycling and drop testing have been confirmed at a large OEM in the handset market.
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 Figure 2. X-ray imaging of 2-die stacked CSPs, one tool used to evaluate the mechanical reliability of test units. |
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A lot of four-high CSP stacks was taken to failure in the thermal cycling test. The results are summarized in the Weibull plot (log-log of cumulative failure vs. number of cycles) shown in Figure 3. The straight line indicates a typical “wear-out” mechanism, rather than sporadic, varied failures. Extrapolation indicates a 1 percent failure rate at 2,100 cycles, which compares favorably with other published results for stacked packages.
 Figure 3. A Weibull plot illustrating summarized results of a lot of four-high CSP stacks that was taken to failure in the thermal cycling test. |
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In general, the results indicate that this design of stacked CSPs meets the reliability requirements for portable electronics. The single failure in a drop test occurred with Pb-free solder balls, and it reflects recent independent findings from IBM Research Center and Texas Instruments Japan showing that the mechanical properties of some Pb-free alloys are not optimized for mechanical shock performance. As shown in Figure 4, the microstructure can be significantly different.
Reliability Issues
Potential concerns with the stacked CSP packaging scheme include reliability of stacked solder joints, reliability of Pb-free (Sn3.0/Ag0.5/Cu) solder in comparison to eutectic Sn/Pb, and the effect of additional package mass and height during mechanical shock or vibration.
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 Figure 4. Microstructures of Pb-free alloys can be significantly different; some are not optimized for mechanical shock performance. |
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The vertical stacking of solder joints does not constitute a reliability concern from the thermal expansion mismatch perspective. There is, however, a concern that the integrity of the multiple solder joints could be compromised if warpage of one or more stacking layers were to occur during stack assembly or surface mount reflow(s). Specific engineering and design measures were taken with the µZ-Ball Stack to minimize warpage, and the moisture sensitivity and thermal cycling test results show that this is not a reliability concern.
Sn/Ag/Cu solder is being evaluated in Japan, Europe and the United States as a Pb-free alternative to eutectic Sn/Pb solder. Data in the open literature suggests than the thermo-mechanical reliability of this Pb-free composition is as good as or better than eutectic Sn/Pb. The mechanical performance of Sn/Ag/Cu, however, is less widely reported, and this is of particular importance for higher mass stacked packages. Currently available drop test data for these packages have shown somewhat better mechanical robustness for the eutectic Sn/Pb solder vs. the Pb-free, but final conclusions cannot be drawn at this point, and further testing is planned. Likely solutions to any potential issues include alloy modification and process optimization.
Vertical stacking of chips inevitably results in increased loads on BGA solder interconnects. The effect of the added mass becomes most significant during mechanical shock or vibration testing because the force transmitted to the BGA solder joints as a result of accelerations will be proportional to the mass of the package. The potential for BGA solder joint fracture or PCB pad failure cannot be ruled out, but the mechanical test results so far have shown that for the 2-die stacked packages, mechanical failure of interconnects is not a significant problem. The results for larger stacks are less extensive, so more work needs to be done, but the results (Table 3 and Figure 3) are quite encouraging. If any mechanical reliability issues do arise with taller stacks of CSPs, measures such as increasing BGA ball or pad sizes, changing pad geometry, and/or adding mechanical balls could be taken to minimize the potential for mechanical failure of BGA interconnects.
Conclusion
There currently is great interest in designing semiconductor packages for use in portable electronics. The CSP format is appealing because of performance and density benefits, and stacked CSPs provide more advantages. The µZ-Ball Stack technology is one CSP stacking approach that has shown excellent performance in reliability testing for portable electronics products.
*µZ-Ball Stack is a registered trademark of Tessera Technologies Inc.
**µBGA-W (wirebonded µBGA) is a registered trademark of Tessera Technologies Inc.
***Dow FA60.
****Dow Corning JCR6224.
References
For a complete set of references, please contact the author.
JEFFREY C. DEMMIN, director of product marketing, may be contacted at Tessera Inc., 3099 Orchard Dr., San Jose, CA 95134; (408) 383-3691; Fax: (408) 894-0768; E-mail: [email protected].