October 1, 2003 – South Korea’s Samsung Electronics Co. Ltd. has developed 4Gbit NAND Flash memory using 70nm process technology, and a 512Mbit DRAM device using 80nm processes.

The NAND memory has a cell size of 25nm cell size, and also features 300-angstrom tungsten gates, which Samsung says it can adapt for designs of up to 50nm.

The DRAM device uses a 3-D recess channel array transistor technology, which builds a 3-D transistor to pair capacitors and enhance density. The chip also incorporates low-resistance tungsten gates, and a high-k oxide process.