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Mid-4Q updates: Happy holidays for chipmakers

Halfway through the current fiscal quarter, several big chipmakers are spreading holiday cheer with revised financial outlooks &#8212 but one chipmaker will also receive a lump of coal in its stocking.

Thanks to better than expected chip sales across all geographic markets, Intel says 4Q03 revenue will come in at $8.5-$8.7 billion, toward the higher end of previous projections of $8.1-$8.7 billion, with gross margins up slightly to 62%. A year ago, Intel posted $7.16 billion in revenues and a profit of $1.05 billion. However, a $600 million impairment charge in its cell phone business will drag down overall 4Q results.

“It’s one of those quarters where you’d like to celebrate the business, and you’re looking at the fact that you have to write off,” said CFO Andy Bryant, quoted in an AP story. The charge is related to Intel’s acquisition of DSP Communications in 1999, which is being written down due to reduced growth expectations.

Investors weren’t overwhelmed with the added charges or outlook, which did not increase the top range of previous forecasts. Intel’s stock , which had seen gains earlier in the week, sank 3% after the news.

Also, at a recent analyst meeting in New York, Intel CEO Andy Barrett said customers outside the US are beginning to reinvest in IT. In reports from Dow Jones and Reuters, Barrett said that as much as half of Intel’s business will come from overseas and emerging markets, where Intel expects to achieve double-digit growth even if the overall market remains flat. “Hopefully, we’ll start to see some enterprise growth in 2004,” said Barrett.” We’ve seen some sprinkling signs of that, but I don’t expect a major, major upgrade cycle.”

AMD says that a build-up in demand that started in 3Q is carrying over into 4Q. “Christmas will happen; demand is definitely there,” said CFO Robert Rivet, according to Dow Jones. Rivet pointed to sales of consumer electronics such as mobile phones with camera features. Rivet also said that AMD’s microprocessor business would see a seasonally strong quarter.

Texas Instruments has upgraded its 4Q03 projections due to continued strong demand, particularly for wireless applications. TI now projects overall revenues of $2.64-$2.77 billion, higher than previous estimates of $2.49-$2.70 billion, and 22%-28% above 4Q02. For its chip business, TI expects $2.33-$2.44 billion, compared with earlier projections of $2.19-$2.37 billion. Earnings are expected to be $0.25-$0.27/share (including $0.07/share from the sale of Micron stock), nearly double its previous estimates, and compared with a $600 million loss last year including items. Ron Slaymaker, VP of investor relations, cited particularly strong demand for chips used in wireless devices, while acknowledging that “most major semiconductor lines are expected to show double-digit sequential growth,” according to Dow Jones. “We don’t see inventory building anywhere in the channels,” he added, suggesting that the growth is not due simply to customers stockpiling inventory.

For its fiscal 2Q04 which ended Nov. 23, National Semiconductor reports net income of $65.8 million &#8212 including a $5.3 million charge &#8212 compared with $6.2 million a year ago. Sales of $473.5 million are up 12% from a year ago, and worldwide bookings were up 36% due to higher demand for computers, displays, and wireless communications devices. It was National’s strongest bookings quarter in three years, according to Brian Halla, company chairman, president, and CEO. “Sales are up, expenses are down…we are ahead of the goals we set for ourselves.” For the third quarter, typically a soft one for National Semi, the company said it already has a higher backlog than anticipated, and expects a 3%-5% overall increase in revenue.

Fairchild Semiconductor has raised its 4Q03 revenue outlook to 8%-10%, up from earlier projections of 6%-8%, with order growth across all end markets. Bookings were especially strong in October and November, raising the backlog “significantly higher” than the end of 3Q, said Kirk Pond, chairman, president, and CEO, with particular strength in the computing, industrial, and communications infrastructure markets. Utilization rates are above 85% with some facilities above 90%, added Hans Wildenberg, executive VP and COO. However, Pond said that the company still needs a strong holiday sales period to extend the current growth phase into 1Q04.

Looking ahead to 2004, STMicroelectronics says sales will be up as much as 20% next year, and the company is expecting to grow even faster to boost its market share. “The upturn this time is robust,” said Chairman Pasquale Pistoro, in an interview with the Frankfurter Allgemeine Zeitung. STMicro is also interested in expansion via acquisition, particularly in the US or Asia, “if the opportunity…were to arise.”

From Productronica: New packaging technologies lead out of the downturn

Ahead of the front-end as usual, sales of back-end packaging and assembly equipment have been recovering quite nicely. But the post-downturn marketplace is a changed one, as demand moves to array packaging and to the outsourcing service houses.

Gartner Dataquest projects sales of packaging and assembly equipment will be up more than 25% this year, and should see 35% growth next year, driven by consumer applications demanding smaller, lighter, and cheaper packaging. “The transition to new array packaging is leading out of the downturn,” said Gartner VP of research Jim Walker. “Just like the last big downturn in 1985-’86 coincided with the shift to surface mount technology, this downturn caused the shift from surface mount to chip-sized packages, ball grid arrays and quad flat no-lead packaging.” He figures these sea changes are not just coincidence, but are the result of companies’ aggressive R&D and cost cutting measures during the downturn.

Accordingly, the recent Productronica exhibition in Munich, Germany (see WaferNews, V10n48, December 1, 2003), was replete with what show organizers and some observers said were the most new technologies they’d ever seen there, heavily weighted toward smaller, lighter, and cheaper.

Datacon Technology, in one such example, aims to reduce flip-chip packaging costs with its new bonder that it says increases throughput by at least 40%. The company has invested some 6 million euros to develop a new bonder from scratch. “We redid it from the design up because the old one was too expensive,” says president Helmet Rutterschmidt. “Every screw is new.” The new version, still being shown to customers only on video, reportedly increases throughput from 7000 to 10,000 units/hour for low I/O smart-card type applications, and from 900 to 2500 units/hour for higher I/O count microprocessors. The company also moved production to Hungary to reduce costs. “China was too much of a leap for us,” explains Rutterschmidt. “Hungary is only a 45-minute flight away, they speak French, and they don’t go on vacation for all of August.” The company notes it also added five new customers in Taiwan this year for its new special-purpose tool for assembling lenses on chips for CMOS image sensors, developed with STMicroelectronics.

Datacon has been doing reasonably well largely on technology buys, and looks for about 25% growth for this fiscal year ending March 2004. Rutterschmidt expects higher growth next year, from growing demand for its flip-chip tools for more applications as costs come down, especially for consumer equipment. He notes the highest volume flip-chip application has now become SAW filters for cell phones, since the industry’s largest supplier switched over its packaging technology this year. His company is also selling tools to the big European chipmakers for smart cards and smart labels.

Gartner projects a 35%-40% compound annual growth rate over the next five years for the flip-chip market, which would move the technology from 3%-4% of the total packaging market now to perhaps 10%.

Wire bonding is seeing new life, too, with the “leadless” leadframe packaging, the chip-sized quad flat no-lead package going into everything wireless. “The rate of adoption of the QFN has been faster over the last 18 months than that of the small-outline IC package in the 1980s,” said Gartner’s Walker. “Capacity is very tight.” He notes, “Equipment suppliers have seen a real nice change in the last six months, with increasing purchases of low-loop wire bonders for CSPs and BGAs.”

“Our orders have really picked up in the last five weeks,” concurs Charles Vath, ASM Technology Singapore’s VP of process and packaging technology. “We’re now booked up solid through January.” ASM’s new wire bonder does 35-micron pitch wirebonding with 15-micron wire, and Vath says the company has a 30-micron pitch bonder in the lab for introduction at the end of the year and a 25-micron pitch model for next year. But that may be getting close to the limit of wire technology. “Twenty-micron pitch isn’t practical,” says Vath. “The wires are too small to carry the current.”

Also apparently starting to make inroads in Europe is Disco’s new dicing-before-grinding technology, which allows dicing of very thin wafers without damage. Infineon has purchased the set of five tools for the new process, which involves sawing the dice apart halfway through from the top of the wafer, then grinding down the wafer from backside to that cut, leaving the chips to fall apart neatly singulated.

Despite the common view that advanced packaging is moving closer to the fab, thus far it looks more like advanced printed circuit board technology is moving up into the chip packaging world. Assembling packages into stacks, multichip modules, or systems in a package essentially is creating a miniature PCB, bringing the chip assembly house closer to what an electronics manufacturing service company traditionally does. “Both groups are increasingly competing for the same marketplace,” says Gartner’s Walker.

This also means a surprising amount of new chip packaging technology is moving upstream out of the PCB surface mount technology world. FEINFOCUS, for example, was showing at Productronica a new wafer bump inspection tool that basically is an upgrade of its x-ray board inspection tool for the chip market — to automatically inspect wafer bumps for voids. While other optical technologies inspect the shape and size of wafer bumps, there isn’t any way currently to inspect the true amount of solder mass. “People may not even know they have voids in bumps,” says Udo Frank, FEINFOCUS director of R&D. “But the solder mass determines reliability.” He says the company now has one of the tools at a user, and one in its lab for customers to see.

Similarly, Asymtek had adapted a technology from its SMT PCB business to the flip-chip world for its new jet-on-the-fly system for adding underfill. The company says the approach shoots dots faster than a needle but applies more material than a spray.

On a more disquieting note, it looks like there are going to be fewer customers for all this proliferating new technology, as high-end packaging moves increasingly to the handful of big packaging and assembly service houses. “More companies are outsourcing the high end right away,” says Datacon’s Rutterschmidt, “even in Japan.” Dataquest’s Walker notes that more than half of the revenues of the outsourcing industry’s top five companies now come from advanced packages like CSPs and BGAs. This suggests fewer, bigger customers to buy most of the new, high-margin tools from crowds of suppliers who are all scrambling to establish their own new approach. Some 32 suppliers were showing bonding tools at Productronica; 18 had flip chip bonders alone — and that was mostly just the European folks! — P.D.

Cooperative efforts focus on advanced packaging opportunities

Productronica, held in Munich, Germany, Nov. 11-14, was overflowing with interesting new advanced packaging technologies on display — and an equally interesting range of cooperative efforts to move European research developments more effectively out of the lab and into the fab. Projects ranged from a new “fabless” package design effort to make better use of European technology, to a city focused on creating MEMS startups.

The latest EU effort to build up its high-end packaging business is a new “fabless” package design house tentatively called PI3, for Packaging and Interconnection Industrial Initiative. The design house is intended specifically to make better use of the scattered-packaging technology and production capacity already available in Europe. Judging that packaging is becoming ever more important for chip performance, an increasingly important portion of the value-added, and more and more closely tied to chip production, the EU funded a project to come up with a business plan to recreate the industrial-scale advanced packaging industry in Europe. The result is an attempt to build a federation of existing companies to help them reach critical mass, using a fabless venture that designs packages to user requirements, drawing on available European technologies and then outsourcing production to existing European packaging companies.

“We saw really strong R&D in Europe in advanced packaging and MEMS, but at the end of the day we were very weak at putting it into practical operation for production,” said Jorge Vieira da Silva, president of Marketing and Technologies Avanc


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