By combining pre-processed wafers from TSMC — up to metal level 2 — and then providing custom programming for as many as five metal levels, AMI Semiconductor says it can cut the cost of reticles to about one-quarter of the usual cost.
“We make the initial investment once and customers don’t have to pay over and over for a complete mask set as they would have to with a cell-based design,” explained Vince Hopkin, company VP of digital ASICs, to WaferNews. The company, which completed an IPO in September, has made structured ASICs a focal point of its business strategy.
In the structured ASIC process, libraries are used to build the device, just as in cell-based ASICs, except pad counts and the number of gates and amount of memory are set but selectable through programming. In contrast, cell-based ASICs are built from the ground up using standard library elements in an array-based architecture — the elements are not programmed. Having the pre-processed base stock wafers purchased in quantity from TSMC, combined with a set-up that fits small volume production runs, makes the company flexible, according to Hopkin.
Admittedly, cell-based ASICs are still a good deal for companies with high-density (e.g., greater than 5-10 million gates or 10-40 million transistors), high-volume products, but Hopkin says that cost savings afforded by structured ASICs are enabling to companies that have high performance, medium density (5 million gates and below, or 20 million transistors and below) products that need fast time-to-market. For medium-density and below products, FPGAs also work, and the NRE costs associated with them are low at the front end. However, FPGAs are expensive to manufacture on a per-unit basis, according to Hopkin. — Debra Vogler, Senior Technical Editor