IMEC, Sematech, TI join high-k club

December 10, 2003 – The past week has been busy for high-k materials, with three separate announcements from companies and organizations detailing the progress of their research.

The Interuniversity MicroElectronics Center (IMEC) in Belgium has demonstrated the use of high-k dielectrics and metal gates at sub-1nm nodes. The material, which uses TiN or TaN gates and HfO2 as a dielectric, scaled down to 0.8nm thickness for both nMOS and pMOS transistors, with better results in terms of conductance, leakage and threshold-voltage instabilities than polysilicon-based materials. “We are convinced that within our industrial affiliation program we now have all the necessary technology and understanding to bring high-k metal-gate devices to implementation in the next technology nodes and within ITRS timeline specifications,” said Luc Van den hove, VP of silicon process and device technology at IMEC. The research was done in collaboration with International Sematech, Renesas, Matsushita, and Samsung.

Also, International Sematech, Austin, TX, has qualified a high-k baseline process at the 85nm technology node, to be used as a comparison standard for ongoing metal gate development. The baseline, which uses hafnium silicide, was achieved by ISMT’s Front End Processes division, which has been working on the material for more than two years. ISMT has built a functional high-k/metal gate device using the material.

And Texas Instruments made a splash at the International Electron Devices Meeting (IEDM) in Washington, DC, with a pair of announcements. The first results demonstrated the viability of a hafnium silicon oxynitride (HfSiON) high-k dielectric material with 90% of the mobility curve of silicon dioxide with “dramatically lower leakage current.” Also at IEDM, TI said that in collaboration with the Swiss Federal Institute of Technology of Lausanne, it has developed a combination of single electron transistors and standard CMOS transistors that can perform logic functions on a much smaller scale than CMOS alone. Shrinking CMOS configurations with field-effect transistors is expected to eventually create problems with signal integrity and heat dissipation. The next step, says TI, is to manufacture onto silicon many SETs in a CMOS-compatible process, with initial uses in memory and metrology applications.


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