On Nov. 4, Intel Corp. announced that Intel Fellow Robert Chau would present results of the company’s high-k/metal gate transistor development at the International Gate Insulator Workshop in Tokyo, Japan, on Nov. 6. The new high-k gate materials are needed to reduce current leakage as device dimensions shrink and transistor gate dielectrics become thinner. Two days after the announcement, Intel updated its data with better results for NMOS high-k /metal gate transistors.
For five years, Chau has led a dedicated team that worked on solving the problems inherent in the search for new gate dielectric materials and integrating them with metal gate electrodes.
According to Ken David, director of components research at Intel, the most significant advancement that eliminated of voltage pinning and phonon scattering was selecting the correct materials for the gate electrodes. Intel had an internal model of what caused these problems; when the correct materials were selected, the problems disappeared.
In his workshop presentation, Chau presented experimental evidence of phonon scattering in high-k materials and cited the possibility that metal gate electrodes may be able to screen the high-k SO phonons from coupling to the inversion channel charge carriers and reduce the mobility degradation problem.
The metals — which remain confidential — must have work functions that match the properties of the polysilicon material they are replacing. The metals will be used in combination with the new high-k gate dielectrics for both PMOS and NMOS transistors.
On Nov. 4, the company presented a transistor curve taken from an 80nm NMOS transistor built with the new process and materials that had an I[on]=1.5mA/micron and an I[off]=43nanoamps/micron, at a drain voltage=1.3V. On Nov. 5, the company released updated performance data for its high-k metal gate NMOS transistor: a drive current of 1.66mA/micron, I[off]=37nA/micron (Vcc=1.3V).
David declined to identify the high-k material that was selected, and also did not identify the supplier of the ALD equipment expected to be used in production. He did say there were no special manufacturing challenges to overcome in order to use ALD to make the new transistor. The company does not currently use ALD in its manufacturing processes, but the process technology also is being evaluated for other steps in the company’s manufacturing flow.
Because Intel has what David described as a fairly large materials group that works closely with R&D to ensure that selected materials will be available when needed, he foresees no problems with availability. David also characterized any changes to the manufacturing process as “cost neutral” — essentially changing out one type of tool for an ALD system. He added that some process steps would be going away (e.g., growing oxides, polysilicon deposition).
According to Intel’s roadmap, the new transistors are expected to be in production by 2007 at the 45nm technology node — when it expects to use 193nm/high-NA lithography. David noted that by 2007, Intel anticipates its microprocessors will contain around 1 billion transistors. A Pentium 4 microprocessor has 55 million transistors. — Debra Vogler, Senior Technical Editor