November 21, 2003 – TEL and Clariant Ltd. say they have created a process that helps prevent the collapse of resist patterns when drawn onto silicon wafers.

The jointly-developed surfactant rinse solutions and processes reportedly reduce pattern collapse by more than 90%, and have been verified down to 55nm.

The companies plan to market the rinse supply hardware and process optimization (from TEL) and rinse solution (from Clariant) by the end of the year, with pricing about 10% higher than existing products, according to the Nihon Keizai Shimbun.