In the News

Nanoelectronics on their way

NORWALK, CONN. — For decades, progress in microelectronics has relied on the continued miniaturization of the devices and wiring on silicon wafers. As device dimensions are scaled into the realm of quantum physics, extraordinary changes in chip engineering are required. Nanomaterials such as carbon nanotubes, semiconductor nanowires, silicon nanocrystals or quantum dots, nanoscale magnetic films and switchable molecular structures, are candidates for next-generation memory and logic chips.

According to a report from Business Communications Co. Inc. (BCC), RGB-286 Nanomaterials in Nanoelectronics, nanomaterial-based devices that will make it to market first will be those that can be fabricated using current chip manufacturing processes and integrated with CMOS technology.

Nanoelectronic memory products will see commercialization ahead of nanoelectronic logic products, with silicon nanocrystal nonvolatile memory, a replacement for flash, and MRAM, a “universal” memory technology, leading the pack. There also will be a shift in manufacturing strategy from “top-down” to “bottom-up” fabrication, in other words, from conventional lithographic patterning to new methods of chemical assembly and nanoimprinting techniques.

Nanoelectronic memory products will enter the market as early as 2004, and by 2008 they are expected to generate $30 billion. With advantages of nonvolatility, ultra-high memory density and a low pricetag, nanoelectronic memory products will increase their penetration of volatile and nonvolatile memory market segments during the next 10 years, and by 2013, a market of about $200 billion is possible. Nanoelectronic logic products will likely be in the early stages of market introduction by 2013. BCC projects the market will be about $20 billion at that time.

Shipley, Rodel to become 'Rohm Haas Electronic Materials'

MARLBOROUGH, MASS. —Shipley Co. and Rodel will become Rohm and Haas Electronic Materials, effective February 1, 2004. Together, Shipley and Rodel comprise the more than $1 billion electronic materials business group of Rohm and Haas Co., which provides material solutions to the electronic and optoelectronic industries.

Shipley Co. recently expanded its product range for wafer scale packaging and bump plating materials. The product line expansion includes photoimageable dielectrics for wafer level redistribution, electroplating photoresists and new metallization processes for IC interconnection.

In October 2003, Shipley Co. announced developments in pure tin finishes that optimize processing conditions to minimize tin whiskers and ensure suitable solderability.

Rohm and Haas is a Philadelpia, Penn.-based specialty materials company that makes products for the personal care, grocery, home and construction markets, as well as serving the electronics industry.

Top 10 Fabless Companies

SAN JOSE, CALIF. — The Fabless Semiconductor Association (FSA) announced the top ten fabless companies by Q3 2003 revenue in its On the Fabless Front quarterly publication.

QUALCOMM's CDMA division led all public fabless companies in revenue for the quarter with $504.4 million. NVIDIA was second with $486.1 million, while Broadcom was third with $425.6 million. Others in the top ten included ATI Technologies, Xilinx, MediaTek, SanDisk, Marvell Technology (estimated revenue), Altera and Conexant, respectively.

Fabless revenue during the quarter totaled $4.5 billion, up 7.1 percent sequentially from $4.2 billion in Q2 2003, and more than 26 percent year-over-year from the $3.6 billion reported in Q3 2002.

The FSA also recorded 45 fabless companies involved in merger and acquisition deals, totaling more than $2.6 billion in 2003. One of the more notable merger and acquisition announcements included the $836 million merger of Conexant and GlobespanVirata, announced in early November.

Ten of the year's acquisitions involved fabless companies acquiring other fabless companies, while 35 acquisitions included fabless companies acquiring other technology (semiconductor and non-semiconductor) companies.

On the Fabless Front discusses this information, along with other industry statistics including fabless fundings, fabless financial news, foundry revenues and foundry utilization.

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ChipPAC Takes Six Stacked-die CSP to Market

FREMONT, CALIF. — ChipPAC Inc., a provider of semiconductor assembly and test services, has delivered a six stacked-die chip scale package (CSP) in a thin, 1.6-mm profile. The 17 ¥ 17-mm, dime-sized package, with more than 400 leads, houses a DSP or an applications-specific IC (ASIC) chip, along with flash and SDRAM chips for compact footprint products such as cell phones, PDAs and digital camera applications. Flash and DSP are projected to be the highest growth segments for semiconductors in 2004. An increasing part of this market growth will see the integration of flash and DSP in a multi-die package solution.

ChipPAC's market data indicates that 100 percent of cell phones in 2004 will ship with stacked-die packages, up from an estimated 60 percent in 2003. Growth in stack packages will be further compounded based on a forecasted 480 million handset sales in 2004, vs. the estimated 440 million in 2003.

ChipPac is planning for volume production of its new CSPs in early 2004.

North American Polymer and ICP Market Predicted to Reach $1.6 Billion by 2008

NORWALK, CONN. — The total North American market for conductive polymers and inherently conductive polymers (ICPs) is estimated at 128.5 million pounds with a value of $205.3 million for 2003, according to a report recently released by Business Communications Co. Inc.

This market is expected to climb to 745 million pounds, valued at nearly $1.6 billion, by 2008. The report, RP-235 Conductive Polymers, also predicts that the market will grow at an average annual growth rate of 9.8 percent in volume and 15.3 percent in value.

Highlights From The MEPTEC Roadmaps Symposium

By Julia Goldstein

SANTA CLARA, CALIF. — The Microelectronics Packaging and Test Engineering Council (MEPTEC) recently presented a technical symposium, divided into several market segments with a panel discussion format for each session, on packaging industry roadmaps.

Many topics were discussed during the cost/performance session, including the difficulty of packaging for 90 nm and below, low-K dielectrics, package sizes, flip chip and green packaging. Panelists represented various members of the supply chain: Keith Newman (Sun); Jerry Tzou (TSMC); William Chen (ASE); Steve Bezuk (Kyocera); Dan Loskot (Henkel); and Kim Hyland (Solectron). Overall, the consensus regarding flip chip packaging was that it is often necessary in high-performance applications, though wire bonding can't be ruled out. The ultimate answer for a given application is still the most cost-effective one. The flip chip ball grid array (FCBGA) is destined to replace ceramic column grid array (CCGA) for application-specific ICs (ASICs), according to Newman. With the possible legislative exemption for high-lead solders in the drive to lead-free, the question of whether to aim toward high-lead or lead-free solders for flip chip applications remains open.

As session chair Hem Takiar (Sandisk) pointed out, stacked die is the primary area of focus for memory packaging. It appears there is no limit to the number of die in a stack, with handling of ultra-thin die under control and no potential thermal management concerns. Advances in wire bonding, such as new low-loop processes described by Leroy Christie (ASM Pacific), continue to enable larger stacks. The test industry, represented by Mark Brandemuehl (FormFactor) and Robin Felder (Nextest), would like to see wafer level packaging (WLP) take off because of its potential to reduce cost of test, but it is not a realistic option for stacked packages containing different types of memory devices. According to panelist Kada Morihiro (Sharp), WLP is not currently justified based on overall packaging cost.

Tom Gregorich (Qualcomm) described the current decade as the “golden age” of mobile phones. New technology is a focus, with work on substrates, decoupling and mold compounds at the forefront. Gregorich reported that Qualcomm is using only wire bond packaging and wants to stay away from flip chip as long as it can. Pitch for chip scale packages (CSPs) is changing from 0.5 to 0.4 mm, and Chris Scanlan (Amkor) mentioned the trend away from ceramic and plastic packages toward leadframes. Integrating bare die from multiple suppliers “remains problematic,” according to Scanlan, but the gap is closing in the area of memory die for stacked packages. Gregorich stated that SOC is a great idea but the industry is not heading that direction; customers care about noise, not the number of chips on their phone.

In his “A View from Aerospace” talk, Tom Clifford (Lockheed-Martin) offered an interesting viewpoint that many in commercial markets don't often hear. The trend toward smaller, faster packages is always presented as positive progress, but the aerospace industry doesn't necessarily see it that way. They are concerned about the reliability of “new” technologies (e.g. area array and stacked packages) that have not been proven through years of extensive testing because “our systems must function properly the first time.” For military and aerospace products, a working prototype is insufficient.

The symposium did not bring about any new roadmaps, but it re-emphasized the need for all industry segments throughout the supply chain to work together. For example, one speaker noted the importance of considering manufacturing capacity as part of the roadmap, while someone else pointed out that testing should be in the forefront. Only with everyone in the same room can all aspects be given the attention they need. The SiP vs. SOC debate brought up during the roadmap symposium will be the topic of MEPTEC's next quarterly technical symposium on February 19.

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At the International Microelectronics and Packaging Society's (IMAPS) 36th International Symposium on Microelectronics, held November 16-20 in Boston, Mass., Phillip J. Zulueta was inaugurated as the society's president for the 2004 term.

Outgoing President Peter Barnwell turned things over to Zulueta, saying “I have greatly enjoyed my year as president and am delighted to now repeat my thanks to all those volunteers and staff who have done all the work, then step down and pass the presidency to Phil Zulueta. Unfortunately in 2002 the president's gavel was lost, but I am pleased to be able to donate a new gavel to IMAPS, which I hand to Phil to represent his office. Phil, I am sure you will do an excellent job and I look forward to serving under you as First Past President.”

Zulueta currently manages the Engineering Assurance and Advanced Technology Group at NASA's Jet Propulsion Laboratory (JPL) in Pasadena, Calif. He is also a program element manager with the JPL Assurance Technology Program Office, which focuses on electronics packaging technologies for NASA applications.

Oliver Shon recently joined Honeywell Electronic Materials (Sunnyvale, Calif.) as their new Greater China sales leader. Shon will focus on strengthening the company's position in Taiwan, as well as implementing Honeywell's strategy to support the emerging market in China by delivering outstanding service and value to its customers.

Shon holds a MBA from Pacific Western University, as well as a bachelor's degree in chemical engineering from Chenshiu Junior College of Technology in Taiwan.

Carsem Inc., a Scotts Valley, Calif.-based provider of packaging and test services, announced a new Chief Operating Officer, S.W. Woo. Woo's responsibilities include operations at Carsem's factories located in Ipoh, Malaysia, and a new factory currently under construction in Suzhou, China.

Woo brings to Carsem more than 20 years of experience in technical and managerial aspects of contract assembly and test services. Prior to joining Carsem, he was the managing director and president of ChipPAC's factory in Shanghai, China. He also has held positions with Intel, RCA and Advanced Interconnect Technologies.

James “Mark” Bird
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Amkor Technology Inc.'s (Chandler, Ariz.) James “Mark” Bird, senior director of technical marketing, has received the 2003 Board of Directors Chairman's Award from JEDEC Solid State Technology Association. JEDEC is the semiconductor standardization association of the Electronic Industries Alliance. The award honors directors of JEDEC's board who have exhibited ongoing leadership in the organization and made significant contributions to the association.

Bird was recognized for his leadership roles as vice chairman of the board of directors focused on human resources; founding chairman of the JC-17 committee of MEMS technology; and chief delegate and technical adviser for the U.S. for the IEC-TC-47 and SC-47D International Semiconductor Standards Committees for semiconductor mechanical outlines, quality-reliability processes and test methods. The award also recognized Bird's roles as subcommittee chairman at joint meetings between JEDEC and the Japan Electronics and Information Technology Industries Association (JEITA), and liaisons on joint standards activities between JEDEC and the U.S. electronics interconnection association, IPC.


Palomar Technologies (Vista, Calif.), a manufacturer of automated, high-precision assembly systems, recently received the 2003 San Diego High Tech Award from the American Electronics Association's San Diego Chapter. Palomar was selected in the category of semiconductors, industrial and analytical instrumentation for its technical achievements and community contributions.

ST Assembly Test Services Ltd. (Singapore), an independent semiconductor test and advanced packaging service provider, has announced that its Shanghai manufacturing facility is ready for operations. Located in Purdong, STATS' new facility offers wafer probe and final test services to cater to the growing mixed signal market in China.

Located in Zhangjiang High Tech Park, a hub for semiconductor manufacturers in Shanghai, STATS' facility occupies 25,000 sq. ft. of Class 10K clean room space.

ASAT Holdings Ltd. (Pleasanton, Calif.), global provider of package design, assembly and test, recently purchased 100 Eagle gold wire bonders and one flip chip bonder from ASM Pacific Technology Ltd. (Bilthoven, the Netherlands). The wire bonders will be used to assemble a wide range of IC packages, including fine-pitch ball grid arrays and tape ball grid arrays.

Amkor Technology Inc. (Chandler, Ariz.) and ASAT Holdings Ltd. (Pleasanton, Calif.) signed a comprehensive patent cross-license agreement for their quad flat no-lead (QFN) semiconductor package technologies.

The two companies each hold numerous patents related to the JEDEC standard QFN packaging technology and have agreed to cross-license their QFN package design and manufacturing process technology patents. The agreement includes both Amkor and ASAT currently issued QFN patents, as well as any future QFN patents that may be granted to either party during the term of the agreement. Amkor's QFN product family includes the MicroLeadFrame, while ASAT's product family includes Leadless Plastic Chip Carrier.

Ziptronix (Morrisville, NC) has inked a deal with Sumitomo Corp. and Sumitomo Corp. of America to distribute the company's engineered substrates, MEMS packaging and 3-D ICs in Japan. The agreement provides Ziptronix with access to one of the hottest mobile device markets in the world.

NATEL Engineering Co. (Chatsworth, Calif.) entered the low-temperature cofired ceramics market through its recent acquisition of the assets of Scrantom Engineering Inc. (Costa Mesa, Calif.), a Solectron company. The new company will remain in Costa Mesa, Calif. and become an integral part of NATEL's broad capabilities in microelectronic packaging, according to NATEL. The company's name has changed to Scrantom Inc.


In the December 2003 issue of Advanced Packaging, the article “Thermal Process of Low-temperature Cofired Ceramics” contained two errors. In paragraph four, the fifth sentence should read “Control becomes more critical with larger parts, >8 inches.” The first sentence in the conclusion should read “ a continuous furnace can significantly increase production throughput by using an optimized recipe to achieve a profile within an extremely small process window.”


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