Chipmakers tout Black Diamond, Applied describes new lowk technology

February 11, 2004 – Eight chipmakers were on hand recently in San Francisco, presenting their end products manufactured at the 90nm node using Applied Materials’ Black Diamond lowk dielectric film on the company’s Producer SE platform.

Representatives from AMD, Agere, Toshiba, NEC, Motorola, LSI Logic, Altera, and ATI joined Applied’s President and CEO, Mike Splinter, at the event. Applied outlined its overall lowk strategy, making a case for volume production and highlighting the certainty of the process (including integration and packaging), as well as collaboration efforts.

Applied also discussed development of second-generation lowk film, which supposedly will overcome the classic problem of porous lowk films: decreased hardness as the k value decreases. Farhad Moghadam, group VP, Dielectric Systems and Modules, said that the next-generation technology achieves this goal by managing pore size and pore distribution — which he said were the real issues.

According to Ken MacWilliams, Chief Technical Officer/Chief Marketing Officer, Dielectric Systems and Modules, developing the second-generation lowk film (k approximately 2.4) is at the top of the priority list for the company. It would have to be ready by 2005/2006 to meet ITRS requirements. Moghadam said that CVD technology by itself (which is used to produce the material) is extendible down to k = 1.9.

Moghadam further explained that the second-generation material can be used without incurring process-flow changes, and he emphasized that the tool platform is extendible — re-engineering will not be needed. Regarding the implications of platform extendibility, Splinter commented that Applied expects to amortize its R&D spending over a large volume of tools sold because of broad usage of the lowk technology.

First-generation Black Diamond (k less than 3.0) will be used to about the 65nm node (there is some overlap between generations/nodes), with the second generation being available sometime around 2007 to see the industry through at least the 45nm node. The integration and circuit-performance benefits sweet spot for lowk will be at values less than 2.4, noted MacWilliams.

So far, feedback from end users is that its second-generation lowk material at 65nm will work with end users’ packaging and integration requirements. Moghadam reiterated that the key is having a lowk material that is compatible with the same CMP, the same electrochemical plating (ECP), and the same barrier seed processes that have been used with FSG.

John Yue, TSMC North America’s VP of Technology, said that the current challenges with lowk and packaging at 130nm and 90nm have been overcome, and he expects that learning at 90nm can be extrapolated to 65nm. Essentially, the same type of low-cost, low-stress assembly equipment will be available. Ronnie Vasishta, VP of Technology Marketing and Coreware Engineering at LSI Logic, added that a large process window is making new packaging equipment and materials unnecessary — only slight modifications are needed.

Also of interest is the future of CMP. David Bennett, Director of Strategic Equipment Technology and Alliances at AMD, stated that the company is using its automated precision manufacturing (APM) technology to customize the plating process and manage copper overburden — essentially optimizing copper polishing over the entire wafer. The company has no plans to use other technologies in the near future.

With respect to barrier films, Bennett briefly noted the company is evaluating ALD with Applied and other companies, as well as direct plating technologies for use at the 65nm node. — Debra Vogler, Senior Technical Editor


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