Wafer Thinning Step 3
BY WEI KOH AND EVELYN BALDWIN
With memory clock speed, density and performance continually being pushed upward, packaging and assembly for high-density memory devices such as flash memory, DRAM and SRAM are changing to thin, multi-stack chip scale packages (CSP). This article presents an update of the market and technical trends in the application of packages for memory devices.
The memory module systems considered here include DRAM modules such as dual in-line memory modules (DIMM), small outline DIMM and flash storage modules (compact flash and secure digital cards). The packages used for these modules are shifting from lead-frame-type packages, such as thin small outline package (TSOP), to thinner and smaller chip scale packages, fine-pitch ball grid array (FBGA) and wafer-level packages (WLP). With thin packages and frequency IC devices moving from 200 to 800 MHz, material property requirements become critical. Due to the smaller amount used for thinner and smaller space, material strength, interfacial properties and thermal behavior become important during assembly and reliability testing. These materials include die attach adhesives, substrates, molding compounds, encapsulants, compliant redistribution layer (RDL) backing and solder balls. Further considerations are needed for high moisture sensitivity level (MSL) requirements and the adaptation of lead-free process and materials. Wafer thinning is a critical enabling technology and manufacturing step to allow for thinner CSP packages, such as VFBGA.
Technology Trends
The use of advanced materials is becoming the critical driver to move IC design and performance forward to the submicron scale and GHz speed range. IBM and Intel are using strained silicon technology to increase speed for example, while Intel is using high-k dielectrics and special metal gate to reduce transistor leaks in the fabrication of 65- and 45-nm wafers. In the semiconductor packaging industry, there appear to be few “breakthroughs” in new materials and manufacturing methods. The progress has been more evolutionary — most of the materials used in packages have not changed substantially, albeit various degrees of improvements have occurred.
Memory Card Market. The projected revenue growth of memory cards and modules is expected to increase from $13.9 billion to $43 billion, according to Semico Research. Compact flash, smart media and memory stick are expected to be the dominating formats in 2004. Other formats include multimedia, secure digital and flash USB drive.
Memory Package Trend
The key drivers in memory packaging are form factors, material cost and reliability. More recently, higher signal speed requirements are becoming more relevant as memory data transfer rate is increasing from the 100-200 MHz range to 800 MHz. Therefore, the packaging material's electrical properties and performance become important selection considerations.
 Table 1. Memory packaging trend. |
Table 1 shows the package types used in mainstream memory products today and in the future. For DRAMs, the migration is from TSOP to CSP, whereas for flash memories the migration may be from CSP to WLP. Further down the road, multiple chip stacking using ultrathin ICs may be used in all three types of memories as the memory density goes up and the functionality of various memory become fused together in system-in-packages (SiPs).
Regardless of package type, the key packaging materials and components remain die-attach adhesives, substrate, encapsulants, leadframe and solder balls.
 Figure 1. Example of a wBGA. Courtesy of UTC. |
Material Reliability Requirements. Current and future package material selections are driven by performance and reliability requirements, including lead-free processing, green products, higher temperature tolerance and higher moisture resistance level (MRL). The increasing thinness in many packages results in bulk material in each component that may be stretched only a few micrometers thick. For example, to maintain the overall thickness of an FBGA to 1 mm, as shown in Figure 1, the die attach bond line may become <5 µm. Thus, the interfacial properties of the various materials become increasingly important. So are the thermal mismatches caused by different coefficients of thermal expansion (CTE).
Wafer Thinning Process
The industry drivers to produce thinner wafers are cost, reduced die stress for WLP and form factor enabling in stacked CSP technology. WLP are built using fab wafers in batch processing for decreased cost.
The intent of the WLP is direct attached to a substrate with no underfill. The CTE mismatch between silicon and typical substrates causes thermal fatigue in solder ball joints. Thinning the die allows more flexibility and improved thermal fatigue. If underfills are required, wafer-applied versions offer a low-cost solution to the process.
As an example, a stacked CSP with 4 die stacks and a 1.4-mm package thickness requires a 0.125-mm die thickness, while a 1.4-mm package with 5 die requires a die thickness of 0.100 mm.
History/Definitions
 Table 2. Mohs hardness scale. |
The first use of natural abrasives dates to about 20,000 B.C. Ancient civilizations learned to use emery to polish gems, marble and metals. The first synthetic abrasive, silicon carbide, was invented in 1891. Synthetic abrasives have become the mainstay of the abrasives world, thanks to their performance and cost benefits. Natural abrasive materials include: emery, corundum, diamonds, garnet, pumice, talc, quartz and sandstone. Synthetic abrasive materials include: aluminum oxide, zirconium oxide, ceramic carbide silicon carbide and cubic boron nitride. In 1812, Mohs arranged ten minerals in order of hardness, so each will scratch those lower in the scale (Table 2).
In 1960, the U.S. Department of Defense began pushing the semiconductor industry to replace vacuum tubes in missiles with solid-state ICs. This spurred work to reduce the thickness variation of silicon wafers and provide the smooth mirror surface needed for high-resolution photolithography. The resulting polishing process used colloidal silica and resulted in the birth of chemical mechanical polishing (CMP). This flatness requirement led to the development of the “spin” mount process. In the 1970s, equipment was developed to measure wafer flatness and further process improvements were developed in automation and wafer size capabilities. This form of polishing has allowed solid-state devices to move from individual circuits to the complex integrated circuits of today. More than 40 years later, the same basic polishing technique remains the industry standard. Feature sizes on semiconductor devices began at about 125 µm in the early 1950s, and recently reached 0.13 µm.
The process to turn a single-crystal silicon ingot into wafers uses several abrasive technologies as described in the following steps:
- Slicing: to slice silicon ingot into wafers of thin disk shape;
- Edge profiling/buffing: to bevel the peripheral edge portion of the wafer;
- Flattening: to flatten the wafer's surface;
- Etching: to chemically remove the processing damage in the wafer without introducing further damage;
- Rough polishing: to obtain a mirror surface on the wafer;
- Fine-polishing: final mirror surface.
While device makers continually shrink line widths, the topography and nanotopography of the silicon wafer becomes more important in both the CMP process and backside wafer thinning.
Definitions vary throughout the industry, but common versions are noted here:
Abrasives. A substance used to grind, lap or polish.
Course grinding or stock-removal. Comparable to sanding or grinding, except that sanding and grinding use abrasives, which are fixed (bonded abrasives).
Lapping. The balancing of abrasive grit size and proper hardness or kind of abrasive against lapping time and the pressure of the part to be lapped. The proper balance is achieved when all abrasive particles break down completely into inert sizes, while removing the desired amount of metal and wearing out the abrasive power of the particles.
Polishing. A grit size of 3-6 µm or finer diamond wheels or slurry.
The Process Today
The most common form of wafer thinning is mechanical grinding to remove silicon from the backside of the wafer. Today's production limit for grinding reduces wafers from an average starting thickness of 725 µm to less than 100 µm, although most thin-wafer production averages 250 µm.
After the wafer is sliced from the silicon ingot at a thickness of approximately 700-800 µm, it undergoes the back grinding and thinning processes. Industry trends indicate that the average thickness of a thinned wafer is reduced by almost 50 percent every two years. It is estimated that the ultimate thinning limit is a thickness of about 20 µm, because the active layer of a chip is 5-10 µm. Currently, the average attainable chip thickness is 50 µm, with claims as low as 25 µm being made.
 Figure 2. Lapping process overview. |
In Figure 2, modern grinders rotate the wafer on a vacuum chuck and feed the rotating grind wheel into the backside of the wafer at a precisely controlled rate (or at a controlled force). A typical approach would incorporate a “stock removal” or coarse grinding. This step achieves a major portion of the total thickness reduction by using a grinding wheel with a coarse, 350-500 grit diamond abrasives.
As the wafer thickness is reduced, microcracks can develop that can lead to increased stress points and reduced yields. The stress-relieving step of polishing or fine grinding is added, which uses a gentler grinding with fine abrasives (2,000-3,000 grit) and ductile grinding technology. Another popular approach to stress relief can be performed by using wet-spin etching or atmospheric dry plasma etching processes.
Alternatives to abrasive technologies have been developed, with success in replacing the two-step grinding process for wafer thinning. Change is difficult in an industry that uses 40-year-old technology, despite the advantages. Plasma etch or chemical processing requires specialized equipment, but can offer less stress in the wafer thinning process.
Plasma etching is a dry etching technology that uses atmospheric downstream plasma (ADP). In ADP etching, inert thermal plasma is generated by DC discharge at atmospheric pressure. The wafer is suspended in a chuck with the backside facing down. Two electrodes directed upward, at a 90-degree angle to each other, sit below the wafer. A plasma arc is formed when a DC field is applied between the two electrodes. Reactant is injected to the plasma stream, which uniformly etches the backside of the wafer.
A chemical spin-processor system removes damaged silicon using acidic compounds containing hydrofluoric acid and HNO3. Fracture tests show that after spin-processing, wafers and dies are less likely to break. The difference between this technology and the traditional wet chemical etching is the use of Bernoulli contactless handling. This technique is able to remove the edge stress risers and the microcracks from the wafer's backside.
A major problem in thinning wafers is bowing, when the wafer bends or even rolls up because of residual stresses left in the wafer. Thin wafers also are difficult to handle because they are easily breakable. As wafers become thinner, uniformity becomes more important.
Hurdles
As the semiconductor industry moves to 300-mm wafers, the difficulties increase in achieving high yielding, flat and stress free wafers. A 200-mm wafer will produce 267 dies, while a 300-mm wafer will produce 600 dies. It is critically important to develop new manufacturing processes that allow silicon wafer manufacturers to produce high-quality wafers at a reasonably low cost.
Handling of large, thin wafers leads to yield loss considerations from grinding and downstream processes (detaping, for example). This makes it very difficult to thin below 150 µm on even 200-mm die. Die cracking during assembly and life test have added to this limit. This leads to requirements for new and improved wafer handling tapes/methodologies.
Conclusion
Memory cards and modules are moving to very thin formats such as secure digital (SD) and miniSD cards. Such modules require devices be thinned at wafer level and then packaged in very thin CSPs or assembled directly onto the card format. A detailed description of the wafer thinning process is provided. Presently the most common practice is lapping/polishing, followed by plasma etch. Thinning a 300-mm wafer down to the order of 100 µm thick, with sufficient yield, remains the main hurdle today. Other package materials must meet stringent requirements for better electrical performance at higher data transfer rates in the GHz range and be more tolerant to higher moisture resistance levels due to lead-free processing. In many thin packages, the materials behave like a composite laminate due to more interfaces and less bulk material — making material interfacial properties critical in package reliability.
References
Please contact the authors for a complete list of references.
WEI KOH, director of Advanced Technology Manufacturing Engineering, may be contacted at Kingston Technology Co., 17600 Newhope Street, Fountain Valley, CA 92708; (714) 427-3531; [email protected]. EVELYN BALDWIN, application development engineer, may be contacted at 3M, Electronics Markets Materials Division, 733 Turnpike Street PMB 302, N. Andover, MA 01845; [email protected].