Packaging of low-k Devices



Most advancements in microelectronics are driven by the necessity to produce chips with greater speed and lower power requirements. This quest has spurred development of new processes and materials for assembling and packaging of inherently fragile devices, including the introduction of copper metallization, eventually integrated with low-k dielectric materials.

Despite the many controversies, delays and setbacks in commercializing low-k materials, it appears that the technology is finally gaining ground. In fact, an estimated half dozen semiconductor manufacturers have already introduced 130-nm chips with low-k dielectrics for a variety of applications.

While the industry's focus is currently on the commercialization of 130-nm devices, it is anticipated that low-k materials will find even greater utility at the 90-nm and 65-nm nodes. Applications expected to take advantage of the technology include high-end uses such as traffic management network processors, switching devices, ASICs, clock synthesis chips and others.

One of the early pioneers among chip manufacturers to use a low-k film elected to integrate it with subtractive aluminum interconnects. After introducing low-k technology in 180-nm devices, the company is now in full production mode with second-generation materials (k=2.8) at 130 nm. The firm's electrical data reveal a 20-36 percent line-to-line capacitance improvement using a low-k interlayer dielectric (ILD) vs. high-density plasma (HDP) oxide. Engineers have already qualified Cu/low-k (k=2.8) at 90 nm, with an immediate objective of integrating an even lower dielectric material into 90-nm dual-damascene processing in 2004.

The first production-qualified communications chip to incorporate a low-k dielectric at the 130-nm level was introduced in 2003, and now is being used in third-generation wireless base station equipment. The first graphics processor unit (GPU) with “true” low-k (<3.0) and copper technology also was announced in late 2003 — a device considered to be the first GPU design to demonstrate significant structural changes from its predecessors.

Historically, chip designs have been constructed with an average of four to six layers of SiO2 as the ILD and one passivation layer, often silicon nitride. The number of layers continues to increase and, as manufacturers have attempted the transition to low-k devices, some have integrated a low-k film into just one or two of these layers. Unique to the new graphics processor design is the fact that this is the first chip to use true low-k films (k<3.0) to isolate the bottom six copper levels and then use FSG for the top two levels.

Future semiconductor designs leveraging low-k technology may use a variety of low-k films in one device, rather than a single dielectric material, possibly in conjunction with FSG and standard SiO2. Such combinations result in a tower-like structure, using ILD materials that have different mechanical strengths and capabilities. These complex designs will present another key hurdle, not only for chip designers and their low-k material suppliers, but also for the packaging experts who are tasked with putting the structures into a final package for specific end-use applications.

Packaging Challenges

Few engineers would have predicted the severity of the integration and packaging issues surrounding the use of low-k dielectric materials, which have caused some manufacturers to delay their adoption. Some designers have attempted to avoid the use of low-k dielectrics altogether. However, it is becoming apparent that long-term performance requirements will require end users to adopt the new dielectric technologies, which in turn will necessitate a transition to alternative packaging designs, processes and materials.

There are two common approaches to lowering the dielectric constant of a film. One is through chemical modifications of the materials, such as introducing carbon or fluorine atoms into the molecular structure. These atoms alter the electrical and physical (density) characteristics of the material, effectively lowering the dielectric constant of the final film.

The second approach is to incorporate porosity into the dielectric matrix. Mechanical properties such as modulus and fracture resistance generally degrade as porosity increases in any dielectric film, and this degradation can produce failures in the field. During the packaging process, the thermal stresses experienced from curing materials such as encapsulants and die attach adhesives further contributes to potential failures. Building reliability and acceptable yields into devices based on porous structures has proven to be an enormous challenge, and it is becoming clear that semiconductor design, materials and process techniques all must be optimized for the industry to take advantage of low-k's potential benefits to increase device performance.

One challenge has been to develop low-k films with a lower dielectric constant to increase device density and speed, while avoiding mechanical flaws such as film cracking and delamination. Projects underway at Stanford University and elsewhere are now examining the effects of moisture and temperature on debonding and cracking behavior exhibited by various low-k dielectric materials.

Because of their differences in thermal expansion properties, the metal, low-k dielectrics and barrier films within a device are particularly vulnerable to fracture and adhesion loss during wafer processing and packaging steps. In addition to the thermal expansion coefficient (CTE) mismatches within the device, the actual movement of a chip during operation can exacerbate failures associated with low-k films. For example, Intel has documented that a microprocessor chip can have significant die warpage — up to 12-µm movement — during thermal cycling between room temperature and 100°C.


In the face of the challenges of integrating low-k dielectrics, reducing the physical stress inherent to the materials of construction (and those introduced by changing temperatures and mismatched CTEs) has become a key objective within the industry. It is possible to use special designs to structurally reinforce a device, such as incorporating a “sea of vias,” but many chip suppliers are seeking to achieve this goal through the use of new packaging materials. Because stress-relieving materials technology holds significant potential for helping chip makers reach their objectives on the industry roadmap, materials suppliers are increasing their focus on new, lower-stress materials for redistribution layers, die attach adhesives and encapsulants used for packaging semiconductor devices.

Another hurdle to on-chip process development is the need to assess packaging reliability with devices incorporating low-k materials. A serious problem is presented by the application-specific nature of device and package structures, since there are slight differences in each design, its package, the environment where the device is used and end-user reliability needs. Although the industry uses conventional, industry-wide testing standards, it can be difficult to address the potential problems for every situation.

Material Solutions

In developing new, low-stress materials for semiconductor packaging, several design factors must be taken into account (along with process criteria) to meet the final device requirements for reliability and performance. Performance criteria include factors contributing to a low-stress environment, such as low residual stress and low thermal stress (i.e., minimal stress hysteresis upon thermal cycling). Other important characteristics typically include good electrical properties, moisture resistance and good adhesion to packaging components.

To minimize residual stress, it is critical to minimize the shrinkage of the material during cure. A low modulus in the cured formulation also contributes to lower residual and thermal stress. In addition, high thermal stability of the material is important, as any hardening due to thermal aging is counterproductive to lowering stress.

Ease of material integration is an equally important criterion for building a package. This includes the process of uniformly applying the material at an adequate thickness onto the device, usually by dispensing, printing or photolithography techniques. New silicone formulations have been shown to be compatible with downstream process techniques, such as metallization and etching in flip-chip or wafer-level package designs. Successful integration also requires a material to have high thermal stability necessary to withstand solder-reflow temperatures, which can be as high as 260°C for lead-free solders.

Redistribution Layers. A recently commercialized family of silicone materials helps reduce the residual stress on a wafer substrate by a substantial margin.* These photopatternable materials are highly flexible and able to absorb stresses created by CTE mismatches, making them good candidates for stress buffer layers as well as redistribution layers to package low-k devices at the 130-nm technology node and beyond.

The measured stress of one of these films, fully cured on the wafer prior to dicing, was continuously measured as it was subjected to a thermal ramp from 50° to 300°C. It was held at 300°C for 30 minutes, followed by a cool-down period. The residual stress was reduced to nearly zero at 300°C. Upon cooling, the stress returned to approximately the original value of 6.4 MPa, demonstrating very little stress hysteresis during the thermal cycle. These thermal conditions are within the typical processing conditions used in building a packaged device and clearly demonstrate the robust, low-stress properties of the material. For comparison, commercial polyimides' residual stress value is typically greater than 25 MPa at 25°C.

Figure 1. Wafer-level package design: silicone under bump (SUB).
Click here to enlarge image

To ease integration of these packaging materials, the introduction of a photopatternable capability allows very precise application, uniformity and high resolution over variable thicknesses. Lower cure temperatures also reduce the effect of CTE mismatches within the device, such as between the silicon substrate, copper metallization and the low-k dielectric film, identified earlier as a potential failure mechanism. These new materials can be hard baked at any temperature from 150° to 250&degC, whereas some current materials used for creating redistribution layers require cure temperatures up to 300°C. Figure 1 shows a proposed package structure, utilizing these new redistribution layers as a silicone “pad” under the solder ball, processed using existing wafer-level packaging techniques, which could reduce stress on the silicon device.

Figure 2. Relieving stress. Diagram and modeling courtesy of IMEC.
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The adhesion and flexibility of the silicone in this structure helps prevent warping, which can occur as a result of thermal cycling. The mechanism for stress relief was modeled by the Interuniversity MicroElectronics Center (IMEC), as illustrated in Figure 2, which shows how warping of the substrate and chip is eliminated as the silicone pad elongates and redistributes the effects of mismatched CTEs.

Die Attach Applications. Although liquid die attach formulations have historically been preferred for their superior gap-filling capability in stacked-die applications, the cure stage can cause warping of the die, sometimes so severe that the effect is called “potato chipping.” Any warpage at this point in the packaging process can only add stress to the device, yet reducing stress is the primary objective for packaging devices incorporating low-k dielectrics.

An alternative solution to liquid die attach materials is to use a silicon-based, low-modulus film adhesive as the die attach for adhering either chip to substrate or chip to chip. The pre-cured, dry elastic films are differentiated from competing materials (such as epoxies and polyimides) by their superior flexibility, which translates directly to stress relief. In fact, new silicone die-attach films designed for microelectronic applications offer a modulus range that is literally hundreds of times lower than alternative materials. By reducing the potentially damaging effects of stress for integrating low-k dielectrics into devices, these die-attach materials help manufacturers continue their quest for smaller, faster, denser and more reliable components.

Die Encapsulants. Moving away from organic-based resins such as epoxies or acrylates to a silicon-based material is one way to deliver a lower modulus, protective encapsulant for semiconductor devices. By nature, the silicone chemical structure has greater flexibility than an all-organic, carbon backbone. Another common method for reducing modulus is to decrease the filler content in a formulation, but the CTE for the bulk material typically increases when doing so. Therefore, formulation changes must be thoroughly tested in the final device to confirm that reliability targets can be met.

Since one of the primary reasons for incorporating low-k dielectrics is to achieve higher clock speeds, the dielectric constant and dissipation factor of the encapsulant in the final package also become a key design issue. An encapsulant that offers the advantage of stable electrical properties at widely varying frequencies contributes further to signal integrity.

A specific silicone encapsulant formulation tested for variation of electrical properties had a dielectric constant between 2.84 and 2.99 when tested at frequencies from 50 to 25,000 MHz. The minimal change in dielectric constant and low dissipation factor are an indication of the material's electrical stability.

Figure 3. Stress decoupling in wirebond device.
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Figure 3 illustrates a large memory chip now in production that incorporates the concept of stress reduction using silicon-based materials. The flexibility of the wire bonds and the encapsulant used to protect them, along with the low modulus die attach, help to minimize stress during thermal cycling as compared to more rigid materials. Incorporating these stress-reducing, silicon-based materials for low-k devices may help the package designer reach overall goals of reduced stress and acceptable reliability.


As performance requirements continue to escalate in semiconductor devices, greater demands will be placed on packaging materials for devices that utilize low-k interlayer dielectrics. These new devices will require packaging materials that not only offer physical protection and reduced stress in the final assembled device, but also have the ability to minimize stresses during the packaging process (e.g., through a lower thermal budget). To maintain the current pace of technical advancement and meet time-to-market demands, material suppliers are likely to play a pivotal role in overcoming the challenges of packaging these low-k devices.

MICHAEL E. KUNSELMAN, Emerging Devices marketing leader, Packaging Solutions, may be contacted at Dow Corning Corp., P.O Box 994, Mail #C02300, Midland, MI 48686-0994; (989) 496-6180; e-mail: [email protected]. BRIAN HARKNESS, Global Science & Technology leader for Protective Materials, may be contacted at Dow Corning Corp., P.O. Box 994, Mail #AUB1007, Midland, MI 48686; (517) 496-7003; e-mail: [email protected].

*Dow Corning WL 5351.


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