TI to sample 65nm in 1Q05

March 22, 2004 – Texas Instruments plans to sample 65nm processes for its wireless chips in 1Q05, doubling the density of equivalent 90nm designs while improving transistor performance by 40%.

TI already has achieved functional 4Mbit SRAM memory test arrays, and expects full production will be ready by the end of 2005, the company said.

The process involves up to 11 layers of Cu interconnects integrated with a low-k dielectric (organo-silicate glass, k=2.8), which it already uses at 90nm and 130nm.


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