STMicroelectronics, CEA-Leti, and AIXTRON develop ultra-thin gate-insulation process

May 26, 2004 — STMicroelectronics today announced that ST, CEA-Leti, and AIXTRON have developed an advanced process technology for the creation of ultra-thin transistor-gate-insulation layers for low-power applications at the 65nm and 45nm CMOS transistor technology nodes.

The new process, called AVD (Atomic Vapor Deposition), significantly reduces transistor leakage current by the deposition of high-k gate-insulation material. The three companies are developing new process technology aimed at the 45nm or 65nm technology nodes for low-power CMOS platforms optimized for portable applications.

The results were obtained by the Advanced Modules team of researchers from ST and CEA-Leti at ST’s Crolles facility using a Tricent AIXTRON 200/300 mm bridge cluster tool. The HfO2 deposited layer process was developed in conjunction with AIXTRON, and the wafer processing and the characterization were performed at CEA-LETI facilities in Grenoble.

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