Lithography, 3D interconnects top SEMATECH 2005 to-do list

June 10, 2004 – International SEMATECH has released its top technical challenges for 2005, a list it uses to focus resources toward the most critical of its approximately 90 R&D projects.

The challenges, reflecting member consensus, include:

– Several areas of lithography, including 193 immersion, EUV and mask infrastructures, line-edge roughness, chemically-amplified resists;

– Frontend processes, including advanced gate stack materials, primarily hafnium-based high-k dielectrics and metal gate electrodes;

– Non-classical CMOS, involving infrastructure development for alternative device technologies, including strained silicon, SOI, and double-gate MOSFETs;

– Interconnects, focusing on low-k dielectrics and process compatibility, and 3D interconnects;

– Metrology, manufacturing effectiveness and productivity, and environment, safety, and health issues.

“Each of these challenges corresponds to critical infrastructure needs in lithography, advanced materials, and manufacturing, as identified in the International Technology roadmap for Semiconductors,” stated Michael Polcari, SEMATECH president and CEO.


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