July 13, 2004 – IMEC has launched a new three-pronged research program on embedded RAM concepts for second and higher levels of onchip cache memory for the 45nm node and below.

The program will focus its efforts on three concepts. First is direct-tunneling RAM, using a very thin (1.5nm) oxide flash structure, storing charges on either a floating gate or a charge-trapping layer, with high-k materials in either case to lower write/erase voltages.

Second, IMEC aims to create a ferroelectric field-effect transistor use high-k materials as a buffer layer between the channel and the ferroelectric, also to lower write/erase voltages.

The third focus is on floating-body cells, based on the memory effect in silicon-on-insulator (SOI) devices initially developed at IMEC in 1998, adapted for planar and FinFET device structures. The eRAM project, which complements IMEC’s flash memory project begun in 2000, aims for implementation in silicon by year’s end.