Tower licenses Virage IP for CMOS processes

July 20, 2004 – Migdal Haemek, Israel – Wafer manufacturer Tower Semiconductor has signed a licensing agreement with Virage Logic Corp., a provider of semiconductor intellectual property (IP) platforms, to make Virage Logic’s technology-optimized platforms available on Tower’s 0.13-micron CMOS processes. The technology-optimized platforms are custom-tuned to a target manufacturing process to meet the requirements of complex system-on-chip designs.

Tower customers will have access to the platforms, which comprise differentiated, embedded memories, standard cell logic libraries, and I/O libraries, on Tower’s 0.13-micron standard logic (TS13SL) process, and later support for its 0.13-micron low-power (TS13LP) process. Virage Logic’s Self-Test and Repair (STAR) memory system and its patented Area, Speed and Power (ASAP) logic metal programmable cell libraries will also be made available to customers.

According to Tower USA Inc. president Doron Simon, Virage Logic was selected for the partnership “because of our mutual success in previous technology generations, silicon-proven libraries on our process, and their commitment and focus on delivering highly differentiated IP.”


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