To address this problem, engineers at Georgia Tech’s Center for Board Assembly Research (CBAR) have developed a new data-driven, closed-loop control technology that adjusts equipment parameters in real time, resulting in fewer defects and higher yields.

(August 3, 2004) Santa Clara, Calif.&#8212One of the hottest topics at Semicon West in San Jose this year was wafer-level processing. If you walked around the show floor, it was hard to find a wire bonder, but wafer bumping equipment and materials were everywhere. Semi even hosted an executive panel discussion on “Wafer Bumping Technology Strategies and Status,” where it was reported that today, less than 5% of all die are being bumped, but in the next two to three years it is estimated that 20-30% of all die will be bumped at the wafer level. This increased interest and expertise brings us that much closer to true wafer-level packaging (WLP), which offers advantages such as smaller footprint and increased performance for higher speeds and increased functionality in portable devices.