Intel readies 65nm process technology for 2005

August 30, 2004 – Last week, Intel presented highlights of its 65nm process technology, which the company has demonstrated on fully functional 70Mbit SRAM chips containing more than 0.5 billion transistors (each cell contains six transistors). The news comes only nine months after the company’s disclosure of its first 0.57 sq. micron SRAM logic cell at 65nm.

Mark Bohr, Intel Senior Fellow and director of process architecture and integration, reported that transistors using Intel’s 65nm technology achieved a ~4x leakage reduction and an increase in drive current of 10%-15%. He maintained that Intel’s use of enhanced strained silicon enabled the achievement and, according to his analysis of competitor data released at industry conferences to date, other chipmakers are behind Intel’s accomplishment by at least a generation. Presenting a plot of I[off] vs. I[on], he explained that most competitors’ data at 65nm lies to the left of the Intel curve at 90nm. The 2x transistor density improvement — per Intel’s roadmap — was a result of reducing transistor gate pitch by 0.7x.

Gate capacitance in the 65nm transistor was reduced ~20% by using a smaller gate length (35nm) and a constant gate oxide thickness (1.2nm), which also avoids increased gate leakage. According to Bohr, the combination of higher drive current and lower gate capacitance (which reduces a chip’s active power) in the 65nm device provides an increase of ~1.4x in switching frequency. To reduce the capacitance of the now 8-metal-layer interconnect (one more than the 90nm generation), the company enhanced the low-k carbon-doped oxide (CDO) material it used at 90nm, and also scaled the line length by ~0.7x.

Bohr characterized the transition to 65nm as easier than going to 90nm, because the materials being used now are going on their second round of usage, albeit in enhanced versions. In particular, the CDO low-k dielectric first used by Intel at 90nm is now enhanced for 65nm, with details discussed in a paper to be presented at IEDM later this year. The strained silicon enhancement, however, will not be disclosed at IEDM.

To conduct the 65nm development, Bohr used a mixture of (dry) 193nm and 248nm lithography tools. “Less than a third of the tools used were 193nm and more than two-thirds were 248nm,” he said. Intel had purchased newer-generation, higher-NA 193nm litho tools for its 90nm production and used them along with alternating phase-shift masks. The company is exploring 193nm immersion lithography for beyond the 65nm node — immersion is not needed for 65nm, contended Bohr.

Discussing the relative merits of strained silicon vs. silicon-on-insulator (SOI) technology for improving transistor leakage performance, Bohr reiterated his stance that SOI does nothing to benefit either source/drain or gate oxide leakage — the two largest contributors to leakage. Bohr said SOI only addresses substrate or junction leakage, which is negligible compared with the other two contributors. Furthermore, Intel had studied fully depleted SOI and concluded that its tri-gate architecture was better, he noted.

Production at 65nm will begin at the company’s 300mm D1D fab in Hillsboro, OR, with the line “owned” by the logic technology development group, which first must demonstrate high yield of the SRAM process. The line is run 24/7, and engineers from Ireland and Arizona are there now to learn how to run the technology, which will also be manufactured at the company’s Fab 12 (Arizona) and Fab 24 (Ireland), said Bohr. He added that high volume production is on track for 2005. — Debra Vogler, Senior Technical Editor


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