Technologies for Microdevice Packaging

Packaging Requirements for MEMS and MOEMS

By R. Pelzer, D. Teomim, G. Perlberg and V. Dragoi

Packaging plays a key role in the continuous miniaturization and improved functionality of a wide range of applications and the reduction of production costs of microelectromechanical systems (MEMS) and optical MEMS (MOEMS). The primary targets of packaging steps are not just protecting devices from environmental influences and matching of the gap between the submicron structures of the IC or MEMS device to the PCB feature dimensions. Packaging also is designed to compensate for stress caused by the different coefficients of thermal expansion (CTE) of the PCB polymer and device components, or to enable final testing in an efficient manner. Due to the broad range of applications for MEMS devices, packaging requirements are diverse.

The substantial difference between the IC packaging processes and the MEMS packaging techniques is induced by the different interactions of those devices with the environment. The type of interaction determines the design, packaging materials and the packaging technique. The packaging process also depends on the function of the MEMS itself — size, weight, performance and reliability, as well as price of the product. Market success of the whole MEMS device is predetermined by the way the micro-moving part is protected from harmful influences of the environment, as well as whether it is unrestricted in its interaction with the measured quantity of the same environment. The MEMS package becomes an essential part of the design work, because the package is closely connected with the functionality of the device. Inappropriate choice of the package may result in poor reliability and narrowing of the spectrum of the system's applications. It is not surprising that packaging represents the major part of the cost of the whole MEMS device (30 to 50% of the costs may represent packaging; for some devices up to 80% have been reported).

Key among the enabling technologies used for assembling and interconnecting MEMS devices are: aligned wafer bonding and wafer-bumping techniques, thick film lithography, and vertical 3-D interconnection. The 3-D integration by vertical interconnection can only be achieved due to the high versatility of the wafer-bonding and wafer-to-wafer alignment technologies. The above-mentioned methods can be used for chip-size packages or chip scale packages (CSP) on wafer level. Therefore, they are suitable for high-volume manufacturing, resulting in low price and high yield. Wafer-level packaging distinguishes itself by its use in MEMS components with sensitive and fragile moving parts like micromirrors, cantilevers, gyroscopes and accelerometers, which may be damaged in a dicing step or during handling of the unprotected device.

Wafer-alignment Methods for MEMS Packaging

Due to the high complexity of the demands raised by MEMS-device packaging in the last decade, great interest was focused on development of various wafer-alignment methods for aligned-wafer bonding. Two main categories of wafer-alignment procedures can be distinguished: direct and indirect alignment (Figure 1). The direct-alignment methods allow visual alignment of the two wafers and offer a simultaneous control loop for the alignment result. Some alignment techniques require at least one transparent wafer for visible (glass, quartz or plastics) or infrared light (silicon). Among the most important factors limiting the application areas of such methods are the poor transmissivity of silicon for wavelengths above 1,050 nm and the impossibility of using metal layers. In the indirect-alignment methods, the two wafers are aligned by means of an external reference positioning system. For front-to-bottom side or backside alignment, the top wafer needs alignment keys on the active side (front side) and the bottom wafer needs them on the backside; thus, both alignment structures are facing downward in microscope direction. The alignment marks of the top wafer are imaged, the position is stored and the backside keys of the loaded bottom wafer are aligned to the stored images. Interface alignment is a second method, which is compared to bottom-side alignment, fully compatible with single-side processed wafers. This technique does not need any transparency of the wafers. This so-called “front-to-front” or “face-to-face” alignment uses two pairs of microscopes: one microscope is placed above and the other below the wafer stack. The dual-microscope system focuses on a common focal plane calibrated for each alignment. Each microscope objective observes the alignment key on the surface of one wafer. The main advantage of this method is the very low Z-axis travel range after the optical-alignment step, which allows high alignment accuracy for wafer-bonding processes.

Figure 1. Bond alignment principles: Direct alignment using visible or infrared light, bottom side alignment, face-to-face alignment.
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Total alignment accuracy can be divided into the pre-bond alignment accuracy, which reflects the accuracy of the aligner, and the post-bond alignment accuracy, which includes the impact of the bonding process. Typically, well-optimized aligned bonding processes achieve post-bond alignment accuracy better than ±1 µm across a 200-mm wafer diameter.

Wafer-bonding Methods for MEMS Packaging

Various wafer-bonding processes are currently used in MEMS packaging. The most common approaches are: silicon direct, plasma activated, anodic, eutectic, thermocompression, adhesive and glass frit bonding.

Silicon-direct Bonding (SDB) or Fusion Bonding. SDB is used for bonding two wafers with mirror-polished surfaces, with wafer flatness better than 0.05 µm and a micro-roughness below 0.5 nm. Cleanliness of the samples is of particular importance for this process (ultraclean bond environment). The bond consists of two process steps. After wafer cleaning (e.g., standard RCA cleaning), the wafers are put in contact at room temperature, which gives a weak bond force of around 0.1 J/m2 (due to the Van der Waals forces established between the two surfaces). In a subsequent high-temperature annealing step (typically above 1,000°C), covalent bonds are formed and the bond strength reaches the bulk fracture strength values. Devices manufactured by direct wafer bonding include pressure sensors and switches, accelerometers, membrane pumps, and several others.

As silicon-direct bonding requires high annealing temperatures, new processes were developed to lower the maximum annealing temperature. Plasma-activated wafer bonding is such a process. Prior to bonding the wafers are submitted to a plasma treatment in a controlled environment. After pre-treatment of the wafers, the annealing temperature for which the bulk fracture strength of silicon is reached is about 200° to 400°C. Plasma-activated bonding is a completely dry process, so it can be applied for fully processed wafers prior to the packaging step, even if they contain etched features, mechanically fragile structures or different metallizations.

Anodic Bonding. Anodic bonding uses heat and an electric field to join a silicon and alkali-doped glass wafer together. At elevated temperatures, the alkali oxides in the glass dissociate. The so-formed mobile ions (e.g., sodium) are driven by the electric field toward the cathode, creating an oxygen-rich layer at the Si-glass interface. The oxygen ions are driven to the Si surface by the electric field and oxidize the silicon. The bond strength is high and the process is irreversible. Typical process parameters for Pyrex (borosilicate glass with a sodium oxide content of ~3.5% and a closely matching CTE over a wide temperature range) are temperatures between 350° to 500°C, high vacuum and voltages up to 1,000 V. The packages realized using this process typically are used for hermetic sealing of MEMS and MOEMS, where elevated bonding temperatures, high voltages and sodium contamination do not affect on-chip electronics.

Eutectic Bonding. The eutectic bonding process is based on formation at the interface between the two wafers of a eutectic alloy. The alloy can be formed between the surface of one wafer and a metal film deposited on the second wafer or between metal films deposited on both surfaces. Examples for eutectic systems, used for hermetic sealing of MEMS devices, are Si/Au (eutectic point 363°C at 97wt% Au), Sn/Au, Ge/Au or Si/Au/Al. The actual bonding temperature is about 20°C higher than the eutectic point.

Thermocompression Bonding. Thermocompression bonding is based on metal bond formation when pressing two metal surfaces against each other while heated. By heating the two wafers, the force needed to form the bonds can be de-creased down to a level acceptable for industrial equipment requirements. As this type of bond should result in good electrical interconnects between the devices on the two wafers, the most used metals are Au-Au, Cu-Cu and Cu-Sn.

Polymer Bonding or Adhesive Bonding. Polymer bonding or adhesive bonding uses temperatures up to 300°C, with low vacuum and low force applied to the substrates. Intermediate layers can be photo-patternable polymers like Benzocyclobutene (BCB) or resists like SU-8, with the thickness ranging from submicron up to tens of microns. Adhesive bonding with low-k dielectric polymers like BCB is gaining more attention since they allow for the creation of electrical interconnects between different functional modules (system-on-package). Adhesive bonding has the advantage of compensating for surface roughness or topography, but the process is not suitable for high vacuum encapsulation (below 10-2 Torr) in the MEMS device. Another disadvantage of adhesive bonding is the relatively low alignment accuracy during bonding, when the intermediate layer gets compressed. Despite this disadvantage, the application spectrum is quite large, especially for low-temperature wafer bonding applications.

Glass-frit Bonding. Glass-frit bonding uses a paste (glass powder with solvent and bonder) that can be deposited onto the wafer surface by screen printing. In general, the glass frit is applied to the cap wafer and softened at temperatures above the melting point. At process temperatures typically within 300° to 500°C, the glass material gets glazed. Under high pressure, the glass frit becomes solidified during cooling.

Table 1. Overview of different bonding techniques for hermetic sealing of packages.
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As numerous MEMS devices require vacuum encapsulation, hermeticity is an important parameter. It should be considered that not all wafer-bonding methods that are suitable to form hermetic seals are suitable to encapsulate high vacuum. Requirements for a suitable bonding method include low out-gassing of the materials involved, precise gap control between wafers and a bonding temperature compatible with the devices. Table 1 provides an overview of bonding technologies.

MEMS Packaging Approaches

Figure 2. Manifold absolute pressure sensor, courtesy of Robert Bosch GmbH.
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Single-device Packaging. After protecting the MEMS by the bonding, the moving parts or active components of the wafers are mechanically and contamination protected. For first-level packaging, the wafers are separated into individual units, which can be mounted onto a package case or directly incorporated into an electrical system without a package. Electrical contacts between the bonding pads of the devices and the inner leads of the package housing are produced by thin wires or ball grid arrays (BGA). Figure 2 shows a demonstrative example of a first-level MEMS package. The device is a pressure sensor, covered by a glass-cap wafer. The most commonly used bonding technique is glass-frit or anodic-wafer bonding.

Wafer-level MEMS Device Packaging and Bumping. Wafer-level packaging and bumping is a low-cost batch process for full package fabrication of MEMS and MOEMS, where packaging and electrical connection is completed prior to the singulation of the wafer in the dicing step. This is the main approach compared to first-level MEMS packaging — the electrical interconnection is done on the backside of the device wafer by wafer-level bumping techniques. Several materials are classified for wafer bumping, like solder (eutectic, lead and alpha particle reduced), gold or copper (pillar bumps). From the different volume bumping methods, electrodepositing and electroplating of gold and solder bumps are the most reliable and down-scalable techniques. For this process, a photolithographic step for structuring photoresist or soldermask, which acts as a template for the electroplated or deposited metal, is employed. Wafer-level bumping is typically performed with 5- to 150-µm films to transfer large (20- to 250- µm) features, with tolerances in the submicron range. After filling and striping of this auxiliary polymer pattern, the solder undergoes a reflow process, forming a spherical bump. Under-bump metallization (UBM) is intended to be a precursor for the electrochemical deposition of the bump metal.

Figure 3. A wafer-level CSP for optical devices. The silicon is laminated between two sheets of glass and completely encapsulated in epoxy, while the electrical contacts are routed to the back of the silicon. This leaves the front, optically sensitive side of the silicon exposed for light sensing.
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A process for wafer-level MOEMS packaging* was developed by one company**. The cavity-type CSP is a “sandwich” of a silicon wafer between two sheets of thin glass. The glass cover has two primary functions: it transmits light from the external ambient to the sensor, and it protects the sensor from the environment. The glasses are attached to the silicon by epoxy adhesives. A cavity above each sensor is created by applying a “spacer rim” on the perimeter of each of the dies on the silicon wafer and the top glass. For MEMS applications, an air cavity can be created below the sensor as well. The electrical contacts are extended from the original, top-facing bond pads, through the sidewalls of the package and redistributed with BGA on the rear-facing side of the bottom glass surface. The manufacturing process steps of the package include:

  • Cavity glass: The first step is to create the spacer glass that separates the glass cover from the silicon. A high-performance optical glass is coated with a light-sensitive polymer (resist). A cavity structure is defined around the perimeter of each die using a photolithography process, followed by a curing of the resist (Figure 3a). Prior to bonding the “spacer glass” to the silicon, the cavity walls are coated with an ultra-thin layer of epoxy resin.
  • First bond: The spacer glass is aligned and bonded to the silicon wafer. The bonding energy is either UV or heat, depending on the type of epoxy used (Figure 3b). At this stage, the active side of the wafer, including all optical sensors, is fully protected from environmental contamination, as well as from physical handling damage.
  • Incorporating a mechanical grinding process, the silicon-wafer thickness is reduced from its original thickness of ~700 µm down to ~70 to 160 µm, followed by an etching process in which the dies are separated along the scribe lines (Figure 3b).
  • Second Bond: In this step, a glass wafer is attached to the backside using epoxy resin followed by a curing procedure (Figure 3c).
  • Notch and Redistribution: The wafer is diced from the backside using an application-specific shaped dicing blade. The cut depth is controlled such that the wafer is notched (diced) through but the spacer glass remains intact. During the notch process, the blade cuts through the extend-pad traces and exposes them to future electrical connection. Following the notch process, a metal layer is deposited in the notch groove using 3-D photolithography methods. The metal layer connects to the device-pads cross section, creating an electrical path from the device to the under bump metallization (UBM) (Figure 3d).
  • Singulation: The final steps in the process include a conventional wafer-bumping process (Figure 3e), followed by a dicing-singulation process (Figure 3f).

3-D Integration

Advanced packaging technologies, WLP and 3-D interconnection are promising solutions to achieve more than one layer of active devices. Device stacking is justified by the potential benefits attainable: size reduction, increase in “silicon efficiency,” reduction of signal time delay, reduced parasitic, decrease in power consumption, increase in speed and number of neighboring devices, and extension of bandwidth. There are basically two technologies for 3-D chip stacking of packages, which should help to overcome the limitation of a fully planar integration. The easiest way to integrate modules and chips is the stacked-package approach. The enlarged package area can be used for electrical connection of the single-package modules, accomplished by a redistribution layer. A more advanced method is the in-package die stack or vertical 3-D interconnection integration, suitable for chip-size packaging. This method reduces the wire length between the chips drastically. Key technologies for 3-D stacking include face-to-face wafer alignment, adhesive bonding, via etching and interconnection. Application examples for increased functionality through stacked wafers include memory devices, logic and memory wafer, advanced MEMS, optical and electrical wafer, and analog/digital wafer (mixed signals).

The requirements for a large degree of alignment, and the fact that the IC industry almost exclusively uses single-side processing, are met by high precision face-to-face alignment. The first 3-D stacking technique (the adhesive Cu/low-k 3-D interconnect technique) was developed at Rensselaer Polytechnic Institute (RPI) and is illustrated in Figure 4a. Two processed wafers are bonded face-to-face using a spin-on dielectric adhesive layer at below 400°C. The top wafer is then thinned down to around 10-µm thickness and high-aspect ratio (5:1) via holes are etched through the backside of the thinned wafer to provide vertical electrical connections between the two wafers. In this manner, electrical connections that may have otherwise been several centimeters long are now only a few microns — dramatically enhancing the performance of such circuits.

Figure 4. Schematic view of 3-D chip stacking using aligned wafer bonding with a) dielectric glues (top) or b) copper-to-copper thermo-compression bonding (bottom).
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Another process*** uses so-called “super vias” — vertical vias of 4-µm thickness and around 10 µm in length — for interconnection of the 3-D wafer stack (Figure 4b). The wafers are aligned by IR alignment and Cu-Cu thermocompression bonded by face-to-face 3-D stacking. After backgrinding, chemical-mechanical polishing and etching of the top wafer back to 5 µm, the vias become accessible from the topside, allowing the process to be repeated so that a stack of multiple wafers can be achieved. To produce a flip chip or CSP, bumps can be created at wafer level using thick resist lithography.


In recent years, the MEMS community has learned that besides the need for developing new processes like deep etching or surface micromachining technologies for device manufacturing, packaging technology must become the main focus, due to its high impact on final device yield, reliability and high costs. Starting from first-level packaging and wire bonding via wafer-level packaging (WLP) and bumping techniques, packaging technology has reached a very important stage: 3-D integration of MEMS modules at wafer level.

*ShellOC & ShellMEMS.
**Shellcase Ltd., Israel.
***Developed by Tezzaron.

R. PELZER, technology manager, and V. DRAGOI, chief scientist, may be contacted at EV Group, DI Erich Thallner Strasse 1, 4780 Schaerding, Austria; 43 7712 5311; e-mail: [email protected]. D. TEOMIM, R&D manager , and G. PERLBERG, VP of Engineering and Technologies, may be contacted at Shellcase Ltd., Menhat Technology Park, POB 48328, Jerusalem 96251, Israel.


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