August 9, 2004 – Tokyo Electron Ltd. (TEL) and European research organization CEA Leti have agreed to jointly research and develop front-end-of-line CMOS process technology, focusing on new materials for CMOS gate stacks.

The research, conducted at Leti’s Nanotec300 300mm facility in Grenoble, France, will investigate high-k and metal gate films and related process steps for the 45nm and below nodes. Development will occur on TEL’s Telformula flexible batch thermal processing system and single-wafer Trias system.

The collaboration will allow CEA Leti “to propose new 300mm cutting-edge module integration technology to its collaborative partners,” including Freescale Semiconductor, Philips, and STMicroelectronics, stated Olivier Demolliens, manager of Nanotec300.

TEL has been busy with industry groups recently; in late July it expanded a lithography collaboration with IMEC to include 193 immersion at IMEC’s 300mm facility in Belgium in order to fine-tune resist processing. And TEL’s chairman Tetsuro Higashi has been tabbed as the next chairman of SEMI.

CEA Leti, meanwhile, also has been busy researching CMOS technologies at the 45nm node and below. In June it announced success with partners STMicroelectronics and Aixtron in developing a process technology supporting high-k insulation layers for CMOS low-power applications at the 65nm and 45nm nodes.

It also is participating with Europe’s top chip industry firms and research institutes in the European Commission’s NanoCMOS project. The project, launched in March, aims to demonstrate the feasibility of 45nm-and-below CMOS logic technologies in two phases: exploring development of materials, processes, device architectures, and interconnects for the 32nm and 22nm nodes, and integrating 45nm technologies and 300mm wafer manufacturing, expected to utilize the Crolles2 facility shared by Motorola, Philips, and STMicro.