Monthly Archives: September 2004

Making the Invisible Visible

By GEORGE T. AYOUB

Flux inspection has been a challenge for flip chip and ball grid array (BGA) assemblers because of the inability of inspection systems, including automated optical inspection (AOI), to accurately see the material and inspect it while maintaining line speed. Specifically with respect to flip chips, the inspection of flux is an important part of controlling the process and can prevent costly mistakes. A machine vision solution using ultraviolet (UV) illumination is able to detect defects from flux deposits. This technique replaces the visible AOI light with specialized UV light that matches the properties of the substrate and flux to achieve optimized inspection results.

Importance of Inspecting Flux in the BGA/CSP Assembly

Flux plays a critical role in the process dynamics of BGA/chip scale package (CSP) package assembly.1 A vast range of defects in final assembly can be traced back to poor flux or paste deposition. For example, some of the defects in the final assembly derive from poor flux alignment with respect to the intended pads, insufficient thickness/amount of the flux material, excessive amount of flux, or from smearing. The detection of these pass/fail types of defects (attribute data) at an early stage of the process reduces the assembly cost significantly. Moreover, many manufacturers would agree that it is important to control the process of flux deposition by means of relevant measured variables to detect trends and prevent defects from occurring. This requires a system that is able to measure the key variables of the process (variable data). By providing real-time information on key process parameters, manufacturers can take corrective action and prevent scrap and production loss.

Technology Challenges: Making the Invisible Visible

The process of flux inspection flux has been a challenge to AOI manufacturers because of the inability of visible light to image the flux material well and inspect it. Both high and low angle illuminations in the visible suffer from poor signal-to-noise ratio of the flux, with respect to the background. When the flux is illuminated with UV lighting, however, it fluoresces in the visible and the signal can be captured by means of proper filters designed to eliminate any background light not emanating from the fluorescent flux. Under these conditions, the signal-to-noise ratio between the flux and the background is significantly enhanced. The key to obtaining a good signal-to-noise ratio is the proper design of filters and illumination, which are proprietary, that are adaptable to the flux itself and to the background material (ceramic and possibly FR4) and at the same time able to eliminate the visible background light (Figure 1).


Figure 1. Images under visible light vs. UV light. On the left, this image of parts using standard white light, flux is not visible. On the right, shown with proprietary UV light, flux is visible.
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Challenge: Speed and Resolution for In-line Systems

Image acquisition parameters play an important part in the capability of the system. Two important parameters are the speed of inspection and the proper optical magnification (resolution). Both are related because speed of acquisition is inversely proportional to the number of pixels acquired, which in turn varies linearly with the square of the magnification. Moreover, illuminating small areas require a large amount of light and an adequate number of pixels on target. The requirements to keep up with very fast cycle times coupled with the high resolution were met by using multiple cameras heads, proper illumination using UV diodes and specialized electronics. Multiple camera heads (in this case three are used) extend the field of view from square to rectangular shape, while at the same time not sacrificing the resolution. The specialized electronics allow the camera to acquire in parallel and matches their speed to the processor computing speed. Using UV diodes assures longevity and stability of the system over time, which is extremely important when an inspection program need to run without modification on different systems or production lines.

Defect Detection, Measurements, Variables and SPC

Using UV fluorescence techniques, the system in operation goes beyond the detection of the pass/fail defects attributes, and assists in enhancing yield by means of SPC techniques on measured variables. It measures the position, area, pad area coverage, and brightness of the deposited flux. Brightness is measured by calculating the median gray scale of the paste blob. Although it is ideal to use the height and volume of the flux, these measurements with the UV technique used here are seen to be dependent on the properties of the flux and the background where the flux is being deposited and cannot be trusted in all cases as absolute measurements. There are good logical reasons backed by experiments confirming that brightness correlates with the height of the flux. In effect, the brightness depends on the amount of fluorescent material in the flux and therefore should vary linearly with the volume. This correlation is not always certain, however, but depends on the environment. Therefore, care should be taken when interpreting the measured brightness since other materials may fluoresce also and add to the noise. The method described has proven to be effective in the production environment, utilizing brightness along with position, area and pad area coverage as measurement parameters, thus providing a logical and adequate means for controlling the final quality of the process by means of SPC methods.


Figure 2. Real-time process control data allows the ability to trend and prevent defects.
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In the production environment, real- time process control has proven to add value to the process by following trends and preventing defects from happening and has been an integral and critical part of the system (Figure 2). Depending on the alarm setting, the system is able to stop the line or turn on a yellow or red light for visual feedback to the operator.

Conclusion

The technique described in this article has been tested with more than three years of in-line inspection. The system is process capable with GRR in the range of 2.5 to 8%. It is able to keep up with a relatively fast production line speed, while achieving a low false call rate. By containing defects at this early stage and controlling the trends with SPC, good results have been achieved. Future planned work is to keep enhancing the signal-to-noise ratio and to extend the application of this technique to different substrates and flux types.

Reference

  1. Reliability and Yield in Flip-Chip Packaging, Alan Lewis, Ed Caracappa, Lawrence Kessler, 1998_11_ hdi_flip_chip_reliability.pdf.

GEORGE T. AYOUB, Ph.D, president, may be contacted at Machine Vision Products Inc., 5940 Darwin Court, Carlsbad, CA 92008; (760) 438-1138.

Lead-free Solder Wafer Bumping


September 1, 2004

OVEN CONTROL AND SOLDER MATERIAL CONSISTENCY ARE CRITICAL

BY FRED DIMOCK AND KRISTEN MATTSON

Over the past 30 years, we have learned that lead negatively affects the health of humans and seen strong legislation remove it from gasoline and paints. More recently, governments in Europe and Asia have set deadlines to remove lead from consumer electronic devices that use PCBs. The ban currently is not being applied to high-reliability applications such as military or medical devices, be we all know that will come someday soon. Likewise, many believe that lead-free solder is coming to wafer bump reflow and are beginning to make the transition.

The transition to lead-free solder will affect the entire wafer bumping process from beginning to end. Changing the bump material affects the reflow temperature, under bump interface chemistry (unstable intermetallic compounds), process atmosphere, plating procedures, cleaning methods, fluxes, etc. Add to this the requirement to shrink geometries, as components get smaller and closer together, and you realize that the move is not trivial at all (Table 1).


Table 1. Decreasing micron size forecast from 2003 to 2018.
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The lead-free transition is much further along for the board assembly process. At first, the thought of lead-free processing caused apprehension among many surface mount engineers because they were forced to move into unknown territory. But groups such as NEMI and the Massachusetts Lead-free Solder Consortium have brought together resources from different parts of the industry to help identify the best materials and methods for implementing these new materials.

Much of the lead-free focus for surface mount has been on the tin-silver-copper (Sn-Ag-Cu) system, also known as SAC. Both NEMI and IPC officially named slightly different variations of SAC as the new standard for lead-free solder, with about 4.0% Ag and 0.5% Cu. The new materials require a peak temperature of 240° to 250°C for reflow, instead of the current range of 210° to 215°C for eutectic tin lead solder.

Early adaptors have demonstrated that these SAC compositions are viable for surface mount applications by showing that they can economically and reliably produce good products. There have been challenges of new fluxes and efforts to better understand the effect of nitrogen on cosmetics, but there is no reason to believe that lead-free solder compositions will be different for wafer bump reflow.

Reflow Process Capability Requirements

Oven control and the consistency of solder material are more critical with lead-free solder. The alloy melting and solidification criteria used by NEMI have been described by Rea and Handwerker. In their report, they discuss the effects of compositional changes on the melting range (solidus vs. liquidus) of SAC and demonstrate that slight shifts in composition can affect the liquidus of the solder by as much as 13°C. This large difference highlights the need for solder manufacturers to ensure that the compositions remain consistent from lot to lot, and places more emphasis on oven repeatability and stability.

Tightening the process control on the reflow process can compensate for these expected slight variations in solder material composition. This can be achieved through a perfectly centered peak temperature with minimum variation run to run. If the process window is ±10°C around peak temperature, and you expect a 13°C variation in liquidus temperature, the effective process window becomes only 7°C. Total thermal variation of 3°C or less across a 12-in. wafer at peak temperature will be required for a lead-free process.

Lead-free Ovens

Oven stability and repeatability requirements necessitate control systems that can maintain consistent temperatures and react to changes in load without overshoots and temperature oscillations (Figure 1). Sophisticated PID algorithms are needed. Most modern ovens have these in place, but some may need adjustments or upgrades.


Figure 1. High-performance wafer bump reflow line.
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Another temperature control factor is convection rate. Higher plenum pressure (convection rate) produces increased and more uniform process temperatures. Although higher convection rates by themselves help uniformity and peak temperature, convection without control can make for an unstable process (Table 2). The best way to establish complete control is to regulate the static pressure of the gas through closed loop convection feedback.


Table 2. Convection rates.
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Closed-loop convection provides temperature control, ensuring that constant heating and cooling transfer rates are maintained and repeatable. Closed-loop convection is a forced convection process that uses static pressure to maximize thermal uniformity and repeatibility. No matter what pressure you use, controlling the convection rate guarantees better temperature repeatability, stability and uniformity.

Questions about atmosphere requirements are not easy to answer for surface mount processing, because it depends on the needs in the specific market being sold to. Much of the recent work has shown that SAC solders need a low oxygen nitrogen atmosphere for cosmetic reasons, not performance. Air results in a discolored surface with wrinkles. Wafer bumping requires a smooth surface, thus a stable nitrogen atmosphere with low oxygen content is important. Many ovens can provide a stable nitrogen atmosphere, but to obtain this atmosphere at a reasonable cost, you need a sophisticated gas management system with gas recirculation and precision control.

Flux is an important lead-free solder issue. The higher reflow temperatures mean that fluxes need to be less susceptible to burning and must stay on the parts longer. Many of these solder suppliers have developed no-clean fluxes that work well at the higher lead-free processing temperatures. From an oven perspective, the flux management system must be able to handle increased temperatures and larger quantities of flux. Older or low-end ovens may have inadequate flux collection systems that can quickly become plugged and even drip flux onto expensive wafers. Flux management, however, has significantly improved in recent years.


Figure 2. Reflow process roadmap.
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The challenges organizations will face depend on which side of the wafer bump reflow equation they are coming from. If they are currently using tin-lead eutectic solder with a nitrogen reflow process, they understand most of the flux issues but will have to deal with equipment capability concerns. If they are currently processing high lead in hydrogen, the move will require extensive learning because they will need to deal with flux and nitrogen reflow in addition to equipment issues (Figure 2).

Eutectic Lead to Lead-free Transition

The major difference between eutectic tin-lead solder and SAC lead-free solder is the reflow temperature. The temperature increase of 30°C can affect many aspects of the process and equipment.

Higher process temperatures mean there is a need for higher furnace set points and higher convection rates. If they have a top-of-the-line oven with an excess of power, good temperature control and the ability to work at higher temperatures, the current ovens will work. Low-end ovens that already are working at their limits will need to be replaced, while in-between ovens may be able to be upgraded with simple retrofit kits (consult with the manufacturer).

Higher process temperatures also mean there is a need for slower belt speeds to maintain the same ramp rates. At ramp rates of 3°C/sec., it takes an additional 10 seconds to heat the extra 30°C and another 10 seconds of additional cooling time. With a 5-min. cycle, 20 seconds translates into a 7% decrease in throughput. Higher process temperatures could affect other components and materials on the wafer. If the UBM is temperature sensitive or alloys with the lead-free solder, it may need to be changed.

High-lead to Lead-free Transition

Much of the world's supply of bumped wafers currently is produced using a dedicated high-lead wafer bump reflow process in a hydrogen atmosphere. For these companies, the switch to lead-free will be dramatic. Along with changes in materials and issues with eutectic solder, the largest challenge will be learning to deal with flux.

In the past, manufacturers of large, expensive wafers moved to high-lead solder with the hydrogen-based process because there was little to no residue from the reflow operation. This clean process had distinct advantages, especially when the pitch between balls was small. They went in this direction because flux management at that time was poor and a clean environment was necessary to maximize yields.

Much of the dedicated high-lead wafer bump reflow is done by large OEMs with large-scale manufacturing. A front-end type batch reflow furnace is used by a number of these manufacturers. This type of tool will not be able to make the transition to lead-free processing. The system originally was designed to control at 360°C and does not control well at the lower temperatures required for lead-free reflow (~120°C less). In addition, a major problem is the use of flux for the lead-free process. These batch systems were designed for a clean environment and cannot withstand the addition of flux residue. They are not suited for cleaning or managing the flux contamination.

Conclusion

The lead-free mandate will soon apply to many of our processes and materials. With the lead-free transition on the horizon for wafer bumping, there is a lot of work to do.

A process with precision temperature control is needed. When it comes to precision temperature control for lead-free processing, it is important to control all of the factors that affect the transfer of thermal energy. With more items being controlled, the need for repeatability and reliability increase. One such item is closed-loop convection. Process engineers trying to achieve the most effective and reproducible thermal transfer process, especially for high-temperature lead-free processing, should take a serious look at this.

Those of us in the wafer bump reflow environment can use this knowledge base to help speed up our implementation, but each of us will have our own unique set of issues to deal with.

FRED DIMOCK, senior process engineer, and KRISTEN MATTSON, product manager for Semiconductor Packaging, may be contacted at BTU International, 23 Esquire Road, N. Billerica, MA.01862; e-mail: [email protected] and [email protected].

SUPPORT FOR TODAY'S EMERGING APPLICATIONS

BY VINCE MCTAGGART, LEE LEVINE AND GENE DUNN

A good form factor and excellent electrical performance are enabling flip chip bonding to emerge as one of the high growth areas of semiconductor assembly. Growth of this bonding technique will accelerate as substrate prices fall and a manufacturing infrastructure is developed.

Gold stud bumps with gold-gold (Au-Au) interconnect (GGI) have developed as a niche segment of the flip chip market. Gold stud bumping uses a variation of traditional wire bond technology to generate gold bumps on a wafer.1 After bumping, a wafer is diced and flipped, then thermalsonically welded to the gold-plated substrate. Metallurgically, a monometallic thermalsonic weld has higher strength and reliability than a solder joint produced by conventional flip chip methods.

Joint development of the stud bump and flip chip die attach process, with optimization of all processes, provides a faster development path than a single party development. These partnerships advance the capabilities of the industry by providing a complete solution.

Advantages of Au Stud Bump and GGI

Two dominant forces control product/process development: cost and functionality. Both solder and plated bumps are wafer-level processes. All bumps are produced simultaneously. Independent of the number of bumps/die, wafer production costs are determined by technology and wafer size (larger wafers are more expensive).

Gold stud bumping is a sequential process, with the bonder producing bumps individually. Depending on the process speed and costs, a high-speed sequential process can be cost advantageous over a fixed-cost batch process. Cost-of-ownership modeling outlines all fixed and amortized production costs, determining the fully loaded costs of a process. Figure 1 compares the costs of different process methods. For low to medium I/O devices, stud bumping has significant cost advantages over electroplated or solder-deposited bumps. As next-generation, higher-speed bonders are introduced to the market, cost of ownership improves, making the stud bump process more attractive to a larger class of products. Figure 1 also shows the crossover points among technologies and how UPH improvements in subsequent generations of stud bump bonders lower the cost to bump a wafer, enabling expansion into new applications.


Figure 1. Bumping cost comparison.
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A cost-of-ownership model for a second-generation platform is shown in Table 1. Costs are grouped in three categories: administrative (labor), capital (installation, shipping, training, depreciation and interest) and variable (capillaries, wire, spares, maintenance, utilities). As bumping speed increases, the cost per thousand bumps decreases from $0.26 to $0.14. Typically, variable costs increase with the number of bumps on a wafer. Administrative and capital costs, however, also rise with the number of bumps on a wafer, because the proportion of machine utilization and fixed costs increase.


Table 1. Stud bump bonder cost-of-ownership model.
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The advantages of gold stud bumping and GGI include: lower cost of ownership; infrastructure; flexibility; turn-around time; reliability; higher strength and conductance; no UBM or redistribution layer; and lead-free. In addition to a lower cost of ownership, these partnered technologies demonstrate higher strength and conductance, and a greater flexibility than conventional flip chip methods.

Electrical/Material Advantages

The electrical and materials characteristics of stud bump and GGI provide benefits. Gold resistivity is 80 to 85% lower than leaded and lead-free solder alloys, providing better current-carrying capacity.2 The thermal conductivity of gold is superior to solder, aiding in heat transfer. Unlike solder bumped packaging, stud bump and GGI does not require under bump metallization or an interposer. It's also lead-free.

When dice are small and the coefficient of thermal expansion (CTE) is well matched to the substrate, GGI often does not require an underfill. Underfill is an expensive process required for solder flip chip, because solder is prone to fatigue fracture during thermal cycling.

Stud bumping can produce small, inexpensive bumps at 50-µm fine pitch that are inherently taller than plated bumps. Plating processes have difficulty achieving this capability without additional expensive masking operations.

Applications

High brightness light-emitting diodes (HB LEDs) are experiencing significant market growth. Applications for HB LED markets include automotive lighting, LCD display backlighting, signage and general illumination. The $1.8 billion HB LED market from 2002 is expected to grow to $4.7 billion worldwide by 2007.3 Flip chip attachment plays a key role in delivering the performance to drive this market.


Figure 2. High-brightness LED construction.
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Traditionally, LEDs used wire bond processes (Figure 2). By changing to the flip chip GGI attachment method, several obstacles were overcome. The top wire bond that blocks light is eliminated. Flip chip contacts replace the inherently thin metal current spreading layers, permitting the device to operate at higher power. In the flip chip configuration, light is projected out the backside of the transparent sapphire substrate to enhance light emission. High thermal conductivity and low electrical resistance of the GGI are superior to solder bump flip chip.

CMOS Image Sensors

Another market segment experiencing growth is the CMOS image sensor. Replacing traditional CCD sensor technology in cell phones and digital cameras, this technology is expected to reach worldwide sales of $4.0 billion by 2007.4


Figure 3. CMOS image sensor construction.
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The construction of a CMOS image sensor by flip chip GGI is illustrated in Figure 3. Unlike CCDs, CMOS image sensors are produced by standard silicon semiconductor manufacturing processes. CMOS technology enables a chip design that can integrate additional functions such as A/D, clock and digital logic into smaller packages at lower cost. Their lower power consumption makes them attractive for portable electronic devices. With the cell phone substrate area at a premium, a 3-D design has been developed. A stud-bumped CMOS image sensor chip is bonded to electrodes on the molded interconnect device (MID) substrate with conductive adhesive. Solder reflow temperatures are too high for the MID substrate, so low-temperature gold bonding of stud-bumped die is required. The flexibility of the stud bump and flip chip attach process allows applications that, otherwise, could not be manufactured.

As DRAM.memory migrates to flip chip, driven by higher bus speeds, its low I/O and similar process to CMOS image sensors make it a likely candidate for the GGI process. Digital signal processors (DSPs) also can benefit from the improved electrical performance and small form factor of GGI.

Flip Chip Bonders


Figure 4. GGI market growth.
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The migration from previous 3-mm2, low I/O SAW filters and oscillator devices into new generation 5- to 10-mm2, medium I/O applications is shown in Figure 4. The new, higher I/O and larger applications require greater force and increased ultrasonic energy, which are available in newer generations of flip chip bonders. New tool configurations are also improving coplanarity between the substrate and the tool, ensuring uniform distribution of the bond force and ultrasonic energy for uniform bond strength. Older-generation equipment is unable to achieve the uniform bond strength required of today's high-reliability devices. A comparison of new-generation flip chip bonders with previous generations is shown in Table 2.


Table 2. GGI flip chip bonder capabilities.
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Conclusion

Flip chip bonding is predicted to grow at a compound annual growth rate of 27% through 2008, increasing from 4.5% of the total current wafer production (200-mm equivalent) to 12% in 2008.5 The latest processes for flip chip bonding and newer generations of stud bump and flip chip equipment provide a compelling cost of ownership for this technology.

References

  1. L. Levine, “Ball Bumping and Coining Operations for TAB and Flip Chip” Proc. 1997 ECTC.
  2. Siewert, Liu, Smith, and Juan Carlos Madeni, “Properties of Lead-free Solders Release 3.0,” NIST and the Colorado School of Mines, May 31, 2001.
  3. “LED Market Report from Strategies Unlimited,” Product Release. July 15, 2003.
  4. “Image Sensor Market at a Critical Point, Says Strategies Unlimited,” Press Release. October 1, 2003.
  5. “Neil Moskowitz, private communication,” Prismark Partners LLC, 130 Main Street, Cold Spring Harbor, NY 11724.

VINCE MCTAGGART, product marketing manager, and LEE LEVINE, senior technical staff, may be contacted at Kulicke & Soffa Industries Inc., 2101 Blair Mill Road, Willow Grove, PA 19090; e-mail: [email protected] and [email protected]. GENE DUNN, microelectronics engineering manager, may be contacted at Panasonic Factory Automation, 1703 N. Randall Road 2J-11, Elgin, IL 60123; e-mail: [email protected].

MEMS DESIGN SOFTWARE SPEEDS PRODUCTION

BY MARK DA SILVA

Similar to IC development, packaging costs for microelectromechanical system (MEMS) devices may reach as high as 80% of the total product cost. A well-recognized commercialization barrier, this is a significant technological issue for the MEMS industry and has resulted in custom packaging for each application. Today, there are options for reducing MEMS packaging costs to bring MEMS devices to market faster.

Packaging MEMS components differs significantly from the packaging of microelectronics, which is well established. The primarily difference is because, unlike microelectronics, the functional specification of the MEMS chip is critical to package design. Industry experts also recognize that a lack of attention may be a contributing factor to the overall problem within organizations, as well as externally with industry vendors and suppliers.

MEMS Packaging Complexity

Microsystem packaging involves multiple layers of interfaces enabling connectivity from the chip to the outside world. Any unforeseen effects of a MEMS device on a package can ultimately inflate product development cycles, time-to-market and production costs. To move standard packaging procedures to the MEMS market, multiple effects must be considered at all phases. Beginning with the chip (for example, the MEMS device), to module, card, board and finally, frame gate. MEMS typically contain moving parts that are sensitive to package effects, and depending on the application, often need to interact with the outside world in some way. In the working environment, packages often need to provide a controlled environment that is hermetically sealed to protect against environmental stresses and corrosion, as well as mechanical and electrical isolation to improve device robustness. For all these reasons, the complexity of MEMS packaging becomes dependent on the specific application, forcing designers to either consider these effects seriously and come up with unique solutions or spend time going back to the drawing board.

MEMS devices are fragile and must be protected from damage during wafer-level processes such as dicing and cleaning. Wafer-level encapsulation or protection of the devices during back-end fabrication processes is part of the manufacturing flow for MEMS mirrors and inertial sensors, and is an inexpensive technique for increasing yield. In certain applications, wafer-level packaging (WLP) is sufficient for final packaging of the device.

While MEMS' manufacturing processes are somewhat similar to ICs, the functionality of these systems is different and presents unique challenges for MEMS packaging. In microelectronics, open tool packages may be used for several chip designs as long as they meet size and connectivity requirements, which is quite unlike MEMS packaging. Open tool packages, however, serve as useful starting concepts for MEMS packaging. Combined with wafer-level, die-level packaging or encapsulation solutions, this offers an inexpensive path to MEMS product commercialization.

Packaging During the Design Phase

The complex, 3-D, mechanical (suspended) nature of MEMS makes them sensitive to their package environment, significantly more so than conventional IC products. Currently, MEMS design is focused on the component level using specific MEMS CAD tools that address the inherently complex device design. Although some techniques exist that allow for package device co-design, they assume decisions about the kind of package, size, materials etc. have already been made, which is typically not a straight-forward task. Product design groups rely heavily on the expertise of package designers (with experience typically from micro- or opto-electronics industries) to choose a package based on a variety of factors such as cost, availability, customization, etc., and then design the package based on specifications of the MEMS device. This typically has led product developers to postpone package selection until after the initial device design has been completed, because design modifications are time-consuming, complex, and costly to rectify. This also has led to inefficiencies in the design process because of the time involved per design iteration. Although the industry is starting to recognize the specific differences between MEMS and IC packaging, and the need to protect the MEMS during fabrication, addressing these challenges often requires access to industry-specific tools and know-how that often resides with package suppliers. It is important for suppliers to share data with designers to overcome these barriers.

Reducing MEMS Packaging Co-design Complexity

Until now, there was no simple way to share detailed package design data in the early stages of the MEMS design process. Recent availability of a set of standard open tool IC packages within an existing MEMS CAD tool environment provides detailed package design data in an easy-to-use, accessible environment. New ground has been broken by the collaboration of a package supplier* and a MEMS design tool provider**. These two groups have standard packaging libraries that may be used to select and analyze the effects of a package on a MEMS device in a single environment (Figure 1). The goal is to preempt some of the issues discussed earlier, arising from MEMS packaging, and ultimately speed their commercialization.


Figure 1. This MEMS layout editor can include changes in design.
Click here to enlarge image

Ceramic technology provides superior performance because of its mechanical strength, thermal conductivity and heat durability, and is durable enough for harsh environments and cost effective for the consumer market. Through the availability of open-tooled packaging solutions, MEMS designers have more choices for initial package selection in terms of chip size, number of electrical connection, etc., and to consider the effects of packaging early in the design phase. With access to package geometry and materials data, designers can choose specific package concepts from a variety of package types, initiate performance-based design (such as thermomechanical effects), and modify package data to specific microsystem requirements, to shorten the design cycle, reduce risk and decrease time-to-market (Figure 2). The supplier's packaging libraries are now bundled with a MEMS design software suite. This software is used to develop MEMS-based products. The availability of these package libraries to such a wide group of designers, at no additional cost, will help accelerate the design process.


Figure 2. After simulated modeling, die deformations can be transferred to new anchor models using this software.
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Packaging Library Content

For MEMS design, packaging data is best introduced in the form of 3-D models. The library allows designers to create the 3-D geometry from supplied data, modify the existing provided geometry or import it in standard format. A complete description of the materials used in each package type is available. Since a variety of views exist for the package, it is possible for a designer to modify the package geometry and material properties completely — allowing for custom package design. These custom designs can be sent back to the supplier for feedback or fabrication.

The package library contains models of a variety of open tool packages types including surface mount devices (SMD), side brazes (S/B), pin grid arrays (PGA), cerdips (C-DIP), leadless chip carriers (LCC), flat packs (F/P), and chip scale packages (CSP). Each package model includes material and geometry data (including mesh), as well as the ability to modify these parameters. The library is embedded within this existing software interface, for ease of modeling and analysis, and contains detailed documentation.

During the design phase, the availability of package information enables creation of physically precise packages in terms of geometry and material properties. A package model or several models can be brought up and co-simulated with the MEMS device to predict a variety of typical package effects, such as coupled thermoelectromechanical or thermofluidic effects or coupled RLC analysis. In the working environment, packages experience a variety of loads such as high-G loads, shock impact, electrical currents or fields, operational temperature ranges, ESD, etc., and it is important to understand the effects of these loads on the operation of the MEMS device. The designer also needs to understand the effects of other external stimuli such as noise and vibration. The MEMS designer must be able to observe the coupling between the various subsystems — MEMS, IC, and packaging. System-level modeling is a powerful technique to allow the MEMS product group to couple the various subsystems in a single environment. Elements of the package library can be converted directly into macro-models that are available to system-level descriptions of the product, thereby allowing for a higher level of optimization of the product.

Conclusion

The ability to bring in standard open tool packages for consideration early in the MEMS design phase, offers product development groups a unique way for the package and device designers to communicate within the same CAD environment to solve problems that are unique to the technology (Figure 3). The ability to import or build, analyze and troubleshoot packaging effects on MEMS devices early in the design cycle enables designers to limit product risk and reduce cost. Further, it offers package designers a path to start with an available package and make changes with the microsystem in mind, and to feed those changes directly back to the supplier for custom development if necessary. Ideally, these packaging capabilities are coupled with a complete MEMS design methodology that begins with schematic-based, system-level design and simulation. It will then enable physical design from 2-D layout and fab process descriptions to 3-D geometry..The next step is to incorporate 3-D field solvers for detailed finite element method and binary element method analysis of electrostatics and coupled electromechanics and other properties. Finally, the methodology will produce extractions of reduced-order behavior models for use in standard EDA or other analysis tools. Ultimately, combining this methodology with packaging analysis capabilities will bring MEMS-enabled products to market faster and at a lower cost.


Figure 3. Example of a simulated MEMS package.
Click here to enlarge image

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References

For a complete list of references, please contact the author.
*Kyocera.
**CoventorWare from Coventor.

MARK DA SILVA, Ph.D., manager applications engineering, may be contacted at Coventor Inc., 625 Mount Auburn Street, Cambridge, MA 02138; (617) 497-6880 X249; e-mail:[email protected].

Optical Packaging


September 1, 2004

SILICON HOUSINGS CHANGE MANUFACTURE OF OPTICAL TRANSCEIVER SUBASSEMBLIES

BY JOCHEN KUHMANN, RALF HAUFFE, ARND KILIAN AND GORDON ELGER

Improvements in silicon MEMS technology, wafer level assembly and test enable both the reduction of current packaging costs and reductions in size. This will create valuable bandwidth for new applications.

The photonics industry as a whole is 10 to 20 years behind more mature industries like the semiconductor industry in terms of standardization, cost structure and assembly techniques. The lag is in part due to key differences between semiconductor and photonic packaging. Photonics components require accurate alignment of glass optical fibers, accurate alignment of optical components, hermetic sealing and a greater variety of materials — each with its own properties.

Shifting Market Priorities

During the optical surge of the 1990s, market pull for optical components was so massive that once the active chip was made, little effort was put into optimizing production flow of the completed optical component. As a result, low-volume packaging procedures were used, and the only way to scale-up production was to hire more skilled employees. For 15 years, there has been little change in the basic technology. The result is a gap between perceived value and actual cost.

New demand in the data communications sector is spurring further growth in photonics components for the LAN (local area network) and SAN (storage area network) markets. The industry is facing pressing cost and bandwidth issues, and it must quickly find solutions to avoid losing momentum. In fact, optical chip and module manufacturers recently banded together to create multisource agreements (MSAs) that enable them to provide better compatibility between different designs, securing second sourcing between several suppliers and lower costs.

The main requirements for optical components such as transceiver optical subassemblies (TOSA) and receiver optical subassemblies (ROSA) are protection, interconnection and manufacturability. Today, in data communications, the various forms of metal-based housings, such as butterfly packages and derivates and TO cans, still dominate TOSA/ROSA packaging because there is no simple way to place a component on the substrate material, properly align it with the fiber and hermetically seal it with the necessary electrical I/O connections.

Building on the Silicon Optical Bench

Silicon as a packaging material was introduced in photonics more than 10 years ago, and was described as a “silicon optical bench” (SiOB). Various companies began to apply the concept, either as a submount for edge-emitting lasers containing V-grooves that fixed in place a single mode optical fiber, or in a laser/turning mirror and lens combination.

This article takes the SiOB platform and demonstrates how it can be developed as an effective packaging platform for lasers, including vertical cavity surface-emitting lasers (VCSELs), Fabry Perot (FP) lasers, distributed feedback (DFB) diode lasers and PIN or APD diodes for light detection. Such a platform can be deployed over a range of applications from low-cost data communications systems to high-end telecom systems.

The basic functions of packaging are to connect the components to the outside world by providing suitable interfaces for the electrical and optical signals, enabling them to transgress undisturbed through package boundaries that protect the components from environmental influences like moisture.

Typically, such interfacing is achieved with traditional packages using electrical feedthroughs with metal packages and different kinds of optical feedthroughs or windows. The electrical feedthroughs are insulated with glass or ceramics. The metal packages with windows are housings that contain a suitable lens and a flange for fiber pigtailing outside the housing. Optical feedthroughs for metal housings are achieved by using a fiber or fiber stub threaded through the sidewalls of the package followed by solder sealing (with or without the help of a ferrule).

The concepts described in this article use the “window” approach, where light leaves the package at a right angle to the top-surface of the housing.

Silicon Micromachining

The advantage of using silicon as a package is clear: the existing infrastructure for silicon micromachining, or MEMS technology, makes low-cost manufacturing easily available through a foundry model. Fabrication of silicon-micromachined housings is characterized by batch processing, and replicating the same patterns on a 6-in. silicon wafer. With traditional manufacturing, batch processing ended at the packaging stage, where a large portion of cost for assembly and testing was incurred.

This is not the case with the approach described here. The silicon housing provides a platform for component assembly using pick-and-place, die bonding and wire bonding at wafer level. Manual labor and handling of piece parts is no longer required. This also means that component yield is dramatically improved. Post-assembly functional tests required even for low-cost, high-volume products (such as a simple DC test to measure the laser threshold) can now be executed at the wafer level, allowing more cost reductions.

The functional devices are then solder-sealed with a glass or silicon lid, while the housings are still in their original wafer format. An optical gross and fine leak test is performed, followed by the burn-in of the components (powering the components at elevated temperatures in order to identify faulty devices). After burn-in, the components are inked and diced.

Standardization of micromachined silicon housing also plays a role in cutting costs. Use of additional landing pads and vias to accommodate for various pad layouts for laser and IC enables straightforward coplanar design. If custom design is required, standard silicon can eliminate shrinkage typical of high-temperature cofired ceramic materials — simplifying package design.

Micromachined Silicon Packages and Optical Connectivity

Optical alignment is a large differentiator within the field of optical packaging. Requirements for multimode fibers and single-mode fibers differ greatly. With silicon micromachining, however, the small size of the package and the exact dimension control (offering tolerances below 1µm) add value to the demanding alignment methodologies required.

Laser light emission from within the two telecommunication windows (1320 and 1550) is characterized by a significant beam divergence that is perpendicular to the laser surface. This characteristic requires lenses situated as close as possible to the laser. The configuration necessitates a beam redirection from the horizontal to the vertical plane, using a silicon mirror with a polished surface and an aluminum thin film metallization. A miniature silicon housing facilitates these requirements.

Silicon lenses (planoconvex) or glass lenses can be part of the houseing and/or glass lenses can be integrated into receptacles. With a collimated beam design, optical isolators that are required for DFB lasers in telecom can be integrated into the receptacle. For short-wavelength datacom applications, plastic receptacles are used with integrated lenses.

Advantages of Silicon in Electrical Performance


Figure 1. ROSA module based on silicon, with glass lid,

Integrating Technologies and Reducing Costs

BY JOSEPH ADAM AND MARK BIRD

System-in-package (SiP) technology has grown significantly over the past several years. It was barely mentioned in the National Electronics Manufacturing Initiative's 2000 roadmap. However, it was one of the fastest growing packaging technologies by NEMI's 2002 roadmap. Even though SiP represented a relatively small percentage of the total unit volume at that time, the 2002 roadmap noted that SIP was becoming a common technology in the high-growth Bluetooth, wireless local area network and mobile phone applications (Table 1). By 2004, SiP had grown so significantly that it was added to the roadmap as a new product emulator group (one of seven), which are used to define future manufacturing needs across the entire electronics supply chain.


Table 1. Although wireless applications are expected to continue to dominate the SiP market, substantial market penetration is also expected in areas such as digital, WLAN/Bluetooth and automotive. Source: Prismark, Deutsche Bank, Credit Suisse First Boston and Allied Business Intelligence.
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The ability to integrate different technologies and to reduce total product cost and time-to-market are the prime drivers for SiP packaging. For the wireless markets, SiPs have enabled the rapid integration of SiGe, GaAs, Si and passive devices into single-package solutions that are not possible today with single-chip solutions. In most cases, this approach has reduced product costs, allowing systems to be partitioned into the most cost-effective blocks. For the system company, these highly integrated functional blocks simplify system design, assembly process and test requirements. Stacking logic and memory chips in a single package is another fast-growing application for SiP. These stacked SiP configurations reduce system size and eliminate the cost of individual packages for each die. They also improve signal transmission times and reduce power by minimizing capacitive loads between ICs.

SiPs are supported by OEMs because they want to continue to push more technology back into the semiconductor side of the business, while holding onto extremely high yields and reliability.

There is much discussion, even confusion, about whether system-on-chip (SoC) or SiP is the better approach for system design. They are, however, often complementary. Development of a new SoC requires a significantly greater investment, both in terms of expense and product cycles. Some products simply cannot support the additional cost or do not have a lifecycle that warrants SoC development, making SiP the cost-effective solution. In other cases, however, a SiP may be used in interim products to add functionality while a SoC is being developed. For example, an OEM might design a first-generation product using an SiP; then the next generation will add more functionality — with the use of a new SiP version — and, possibly the third generation will integrate all of the second-generation functionality onto a single chip. At that point, the SiP transforms itself into another package that now supports the SoC and other functions such as antennas, crystals, filters, shields and other passive components that are not part of the SoC.

At present, there are three types of SiPs that are running in high volume: modules, stacked die packages and stacked package on package (see Sidebar for descriptions). Laminate substrate-based SiPs continue to dominate the market, but ceramic, lead frame and tape substrate technologies are growing rapidly.

State of the Technology

Rapid expansion of the SiP market has stimulated research and development in SiP-related technology by integrated device manufacturers (IDMs) as well as electronic manufacturing service (EMS) providers and semiconductor assembly services (SAS). R&D efforts have also led to development of SiP-specific design tools, equipment, materials and components. Like most emerging technologies, however, R&D expenditure has not been increased to the required level in several key areas.

One of the technology challenges for early adoption of SiP was the lack of integrated design tools that would enable chip and package co-design. Several of the large EDA companies and numerous small design tool specialists now have commercial tools available for SiP. As the complexity and performance targets for SiP increase, these tools need to be enhanced to provide faster 3-D electrical and mechanical simulation capability. One area in particular that needs to be developed is the ability to evaluate the impact of manufacturing variance on SiP electrical performance.

SiP technology is pushing equipment and related process capabilities to their limits for SMT, die attach, wirebond and flip chip processes. Equipment companies have started to develop dedicated platforms for SiP applications in some of these areas, which has helped to resolve process capability problems. One of the biggest areas of opportunity for further cost reduction is the development of die attach and flip chip placement. The 2004 NEMI SiP roadmap calls for placement equipment to be able to handle die placements from wafer format with 15-µm accuracy at less than $.005 per placement. Industry cannot meet this target with today's equipment.

In the materials and component technologies areas, SiP is driving new material applications and the related need to develop new qualification requirements. Most SiP technologies are already based on lead-free assembly processes and qualified to MSL Level III 250°C reflow conditions, well ahead of the general electronics industry. As SiP applications continue to grow, the focus on new materials tailored to these applications will be needed to further improve cost and reliability.

As higher complexity, multifunction SiPs are developed, the need for optical and MEMs-based components will also become more significant. These component types use specialty packaging technology, which is difficult to integrate into many SiP configurations due to thickness, size and cost. Low profile, low-cost wafer-level packaging needs to be further developed by industry to resolve these problems.

Infrastructure Issues

SiP technology merges the surface mount technology of the EMS industry with the semiconductor assembly and test technologies of the SAS industry. This convergence thrusts surface mount technology (SMT) and bare die assembly technologies together in a single factory, which poses several challenges and raises critical infrastructure issues that must be addressed. The two groups (EMS and SAS) have different business models as well as different requirements and specifications. Then there are issues of equipment and skill sets.

To hit reasonable profit levels, SAS companies target gross margins in the 20% range, while the EMS companies target gross margins in the 10% range. The difference in these operating models is due to differences in factory overhead (clean room vs. standard manufacturing), R&D, equipment and labor cost. For SiP, manufacturing companies must develop a new operating model that mixes the SAS and EMS structures. This model must also be able to support the industry target of a 15% reduction in product cost per year to maintain competitiveness.


Figure 2. The SiP-based land grid array (LGA) shown here is a fully integrated GSM/GPRS single-package radio that shrinks radio size by more than 2/3 for cellular applications.
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In addition, EMS and SAS operations do not follow the same quality and reliability specifications. EMS providers use IPC board mount specifications while the SAS use JEDEC component specifications. This can create some major differences, depending where the SiPs are built and what is needed for the end market requirements.

Skill set is another big issue. The mixed technology skills required for SiPs are not readily available and require taking specialists from different areas and combining their skills. Typically, a company has to hire one or the other skill set, and then train the individual, which is a two-year process. The industry will need to develop better SiP training forums to help resolve this issue.

Conclusion

SiP technology offers a viable alternative to product designers. While the march to ever- increasing silicon integration continues, SiP provides the ability to mix semiconductor technologies along with other functional components in a package that, in many cases, looks and feels like a single chip device (from the board assembly point of view). Advantages can include increased packaging density, improved supply chain flexibility (i.e., design for postponement), reduced risk (over fully integrated silicon) and lower total system cost. A number of infrastructure issues need to be addressed in order to allow this technology to achieve full potential. Given the margin pressures on this segment, industry collaboration could provide a cost-effective method to close the identified gaps without any one company taking on the full development burden.

JOSEPH ADAM, vice president of strategic marketing, may be contacted at Skyworks Solutions Inc., 5221 California Avenue 31-2, Irvine, CA 92612; e-mail: [email protected]. MARK BIRD, senior director of technical marketing, may be contacted at Amkor Technology Inc., 1900 South Price Road, Chandler, AZ 85248; e-mail: [email protected].

Types of SiPs


Figure 1a This stacked-die SiP, which features memory on top and logic on the bottom, is used for portable applications.
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Stacked-die packages include any standard package with two to five vertically stacked devices with a lead frame, PCB or flex circuit base (Figure 1a). Ideal for memory, this will find some use with logic. In 2003, 500 million were shipped. Growth of 25% is expected.

Stacked package-on-packages include pre-packaged devices that are stacked on top of each other using lead frame, PCB and flex-based solutions (Figures 1b). Stacked die in package could also be used here. It currently is used for high-density DRAM with TSOP. Tens of millions were shipped in 2003. Extension to CSP solutions will increase application areas. They are constrained by high costs and are limited to low I/O density devices.


Figure 1b. This stacked package-on-package FBGA SiP integrates memory with logic used in cell phone applications.
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Modules include LTCC and PCB-based modules that combine one or more die and integrated and/or discrete passive components in a BGA, LGA or castellated joint packages. Ideal for RF applications in cell phones, using a combination of active and passive components. Nearly 1 billion units were shipped in 2003 (PA, antenna switch, transmit, front-end module). They will extend beyond RF.


Figure 1c. This image shows a multichip module. It is a Bluetooth SiP BGA.package used in wireless applications, cell phones and LANs.
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Multichip modules use multiple die and, optionally, passives in side-by-side and stacked- die configurations with standard package outlines (Figure 1c). These are niche solutions for high-end applications, and are often displaced by silicon integration (for example SoCs). They are limited by high substrate costs and known good die issues. High volume will be driven by low-lead-count QFN and lead frame designs for power and other applications.

Source: Prismark Partners.

“Software” is of course a very broad topic, but design and simulation is probably what comes to mind most often when the term is used in our industry. There have been some amazing advances in the capabilities of these tools, although there is still plenty of evidence that reminds us of their limitations.

Impressive Simulation Capabilities

The use of software in solving engineering challenges is increasingly pervasive. I paged through the proceedings of the International Electronics Manufacturing Technology (IEMT) symposium this year to get a feel for how software is being used, but it would have been easier to spot the few papers that didn't use advanced software somehow.

A paper from ASE used finite element analysis to correlate power cycling and thermal cycling fatigue. A paper from MicReD in Budapest used compact dynamic thermal models to evaluate the quality of die attach in stacked die packages. Credence discussed design-for-test software to improve time-to-market. Johnstech and Agilent presented a joint software-based effort to optimize test equipment and contactors to optimize yields. MicroFabrica and SolidWorks discussed how to use mainstream software for design and analysis of MEMS. The scope went far beyond the stress analysis, thermal modeling, and electrical parasitic calculations that are commonplace now.

Limitations

Although the current capabilities of analysis tools are impressive, simulation still cannot match the ultimate accuracy of measurement. The authors of a recent paper in an IEEE journal went to great lengths to show that critical product decisions should not be based solely on simulations.

The June 2004 issue of the IEEE Transaction on Components and Packaging Technologies featured that intriguing article, titled “Numerical Prediction of Electronic Component Operational Temperature: A Perspective.” The authors, from Electronic Thermal Management, CALCE, and Dublin City University, performed some very detailed analysis of the predictive ability of thermal models. Using the latest techniques in computational fluid dynamics (CFD), they showed that there can be significant differences between modeled and measured results for board-mounted components. The main conclusion is that measurements are still required for strategic product design decisions.

The complete list of conclusions in the paper cited above amplifies this point. For example, the authors noted that the accuracy of models of real systems is less than models of standard test cases. The complexity of 3-D flow conditions is greater in actual systems, which decreases the accuracy of the models.

There were other detailed technical conclusions in the paper, and a resulting outcome was the need for thermal analysis specialists to stay involved in the process. The ability to put CFD-scale computation power in any computer doesn't mean that anyone can now do good thermal analysis. Building CFD models, defining grids, and obtaining sound solutions still requires significant expertise in the field.

Software as Product Differentiator

Beyond the design and analysis realm, software is becoming a more prominent factor in process equipment as well. For example, at SEMICON West this year, Phoenix X-Ray announced automated software modules to simplify solder joint inspection and pass/fail determination in QFP and MLF style packages. The company is highlighting software rather than hardware capabilities to differentiate its product.

Recent literature from V.J. Electronix, a provider of X-ray inspection equipment, also focuses on software capability. It cites “advanced defect enhancement” software as an innovation for high-accuracy X-ray microscopy. The latest announcement from August Technology also highlights the company's purchase of defect data management software from Inspex for its inspection and metrology systems.

The trend should be clear. More and more often, software capability is the deciding factor in equipment selection.

The Future

Where will software take us in the packaging industry? I think that the lesson of the IEEE paper mentioned earlier will be a perpetual one. Software advances will continue in design and simulation, and in equipment as we've seen here as well, but the subtleties of what we are trying to do as an industry will stay a step or two ahead of software developers. Human expertise and insight will still be required for the best solutions to our engineering challenges.

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JEFFREY C. DEMMIN, director of product marketing, may be contacted Tessera Technologies Inc., 3099 Orchard Dr., San Jose, CA 95134; (408) 383-3691; e-mail: [email protected].