Integrating Technologies and Reducing Costs
BY JOSEPH ADAM AND MARK BIRD
System-in-package (SiP) technology has grown significantly over the past several years. It was barely mentioned in the National Electronics Manufacturing Initiative's 2000 roadmap. However, it was one of the fastest growing packaging technologies by NEMI's 2002 roadmap. Even though SiP represented a relatively small percentage of the total unit volume at that time, the 2002 roadmap noted that SIP was becoming a common technology in the high-growth Bluetooth, wireless local area network and mobile phone applications (Table 1). By 2004, SiP had grown so significantly that it was added to the roadmap as a new product emulator group (one of seven), which are used to define future manufacturing needs across the entire electronics supply chain.
The ability to integrate different technologies and to reduce total product cost and time-to-market are the prime drivers for SiP packaging. For the wireless markets, SiPs have enabled the rapid integration of SiGe, GaAs, Si and passive devices into single-package solutions that are not possible today with single-chip solutions. In most cases, this approach has reduced product costs, allowing systems to be partitioned into the most cost-effective blocks. For the system company, these highly integrated functional blocks simplify system design, assembly process and test requirements. Stacking logic and memory chips in a single package is another fast-growing application for SiP. These stacked SiP configurations reduce system size and eliminate the cost of individual packages for each die. They also improve signal transmission times and reduce power by minimizing capacitive loads between ICs.
SiPs are supported by OEMs because they want to continue to push more technology back into the semiconductor side of the business, while holding onto extremely high yields and reliability.
There is much discussion, even confusion, about whether system-on-chip (SoC) or SiP is the better approach for system design. They are, however, often complementary. Development of a new SoC requires a significantly greater investment, both in terms of expense and product cycles. Some products simply cannot support the additional cost or do not have a lifecycle that warrants SoC development, making SiP the cost-effective solution. In other cases, however, a SiP may be used in interim products to add functionality while a SoC is being developed. For example, an OEM might design a first-generation product using an SiP; then the next generation will add more functionality — with the use of a new SiP version — and, possibly the third generation will integrate all of the second-generation functionality onto a single chip. At that point, the SiP transforms itself into another package that now supports the SoC and other functions such as antennas, crystals, filters, shields and other passive components that are not part of the SoC.
At present, there are three types of SiPs that are running in high volume: modules, stacked die packages and stacked package on package (see Sidebar for descriptions). Laminate substrate-based SiPs continue to dominate the market, but ceramic, lead frame and tape substrate technologies are growing rapidly.
State of the Technology
Rapid expansion of the SiP market has stimulated research and development in SiP-related technology by integrated device manufacturers (IDMs) as well as electronic manufacturing service (EMS) providers and semiconductor assembly services (SAS). R&D efforts have also led to development of SiP-specific design tools, equipment, materials and components. Like most emerging technologies, however, R&D expenditure has not been increased to the required level in several key areas.
One of the technology challenges for early adoption of SiP was the lack of integrated design tools that would enable chip and package co-design. Several of the large EDA companies and numerous small design tool specialists now have commercial tools available for SiP. As the complexity and performance targets for SiP increase, these tools need to be enhanced to provide faster 3-D electrical and mechanical simulation capability. One area in particular that needs to be developed is the ability to evaluate the impact of manufacturing variance on SiP electrical performance.
SiP technology is pushing equipment and related process capabilities to their limits for SMT, die attach, wirebond and flip chip processes. Equipment companies have started to develop dedicated platforms for SiP applications in some of these areas, which has helped to resolve process capability problems. One of the biggest areas of opportunity for further cost reduction is the development of die attach and flip chip placement. The 2004 NEMI SiP roadmap calls for placement equipment to be able to handle die placements from wafer format with 15-µm accuracy at less than $.005 per placement. Industry cannot meet this target with today's equipment.
In the materials and component technologies areas, SiP is driving new material applications and the related need to develop new qualification requirements. Most SiP technologies are already based on lead-free assembly processes and qualified to MSL Level III 250°C reflow conditions, well ahead of the general electronics industry. As SiP applications continue to grow, the focus on new materials tailored to these applications will be needed to further improve cost and reliability.
As higher complexity, multifunction SiPs are developed, the need for optical and MEMs-based components will also become more significant. These component types use specialty packaging technology, which is difficult to integrate into many SiP configurations due to thickness, size and cost. Low profile, low-cost wafer-level packaging needs to be further developed by industry to resolve these problems.
Infrastructure Issues
SiP technology merges the surface mount technology of the EMS industry with the semiconductor assembly and test technologies of the SAS industry. This convergence thrusts surface mount technology (SMT) and bare die assembly technologies together in a single factory, which poses several challenges and raises critical infrastructure issues that must be addressed. The two groups (EMS and SAS) have different business models as well as different requirements and specifications. Then there are issues of equipment and skill sets.
To hit reasonable profit levels, SAS companies target gross margins in the 20% range, while the EMS companies target gross margins in the 10% range. The difference in these operating models is due to differences in factory overhead (clean room vs. standard manufacturing), R&D, equipment and labor cost. For SiP, manufacturing companies must develop a new operating model that mixes the SAS and EMS structures. This model must also be able to support the industry target of a 15% reduction in product cost per year to maintain competitiveness.
In addition, EMS and SAS operations do not follow the same quality and reliability specifications. EMS providers use IPC board mount specifications while the SAS use JEDEC component specifications. This can create some major differences, depending where the SiPs are built and what is needed for the end market requirements.
Skill set is another big issue. The mixed technology skills required for SiPs are not readily available and require taking specialists from different areas and combining their skills. Typically, a company has to hire one or the other skill set, and then train the individual, which is a two-year process. The industry will need to develop better SiP training forums to help resolve this issue.
Conclusion
SiP technology offers a viable alternative to product designers. While the march to ever- increasing silicon integration continues, SiP provides the ability to mix semiconductor technologies along with other functional components in a package that, in many cases, looks and feels like a single chip device (from the board assembly point of view). Advantages can include increased packaging density, improved supply chain flexibility (i.e., design for postponement), reduced risk (over fully integrated silicon) and lower total system cost. A number of infrastructure issues need to be addressed in order to allow this technology to achieve full potential. Given the margin pressures on this segment, industry collaboration could provide a cost-effective method to close the identified gaps without any one company taking on the full development burden.
JOSEPH ADAM, vice president of strategic marketing, may be contacted at Skyworks Solutions Inc., 5221 California Avenue 31-2, Irvine, CA 92612; e-mail: [email protected]. MARK BIRD, senior director of technical marketing, may be contacted at Amkor Technology Inc., 1900 South Price Road, Chandler, AZ 85248; e-mail: [email protected].
Types of SiPs
 Figure 1a This stacked-die SiP, which features memory on top and logic on the bottom, is used for portable applications. |
Stacked-die packages include any standard package with two to five vertically stacked devices with a lead frame, PCB or flex circuit base (Figure 1a). Ideal for memory, this will find some use with logic. In 2003, 500 million were shipped. Growth of 25% is expected.
Stacked package-on-packages include pre-packaged devices that are stacked on top of each other using lead frame, PCB and flex-based solutions (Figures 1b). Stacked die in package could also be used here. It currently is used for high-density DRAM with TSOP. Tens of millions were shipped in 2003. Extension to CSP solutions will increase application areas. They are constrained by high costs and are limited to low I/O density devices.
 Figure 1b. This stacked package-on-package FBGA SiP integrates memory with logic used in cell phone applications. |
Modules include LTCC and PCB-based modules that combine one or more die and integrated and/or discrete passive components in a BGA, LGA or castellated joint packages. Ideal for RF applications in cell phones, using a combination of active and passive components. Nearly 1 billion units were shipped in 2003 (PA, antenna switch, transmit, front-end module). They will extend beyond RF.
 Figure 1c. This image shows a multichip module. It is a Bluetooth SiP BGA.package used in wireless applications, cell phones and LANs. |
Multichip modules use multiple die and, optionally, passives in side-by-side and stacked- die configurations with standard package outlines (Figure 1c). These are niche solutions for high-end applications, and are often displaced by silicon integration (for example SoCs). They are limited by high substrate costs and known good die issues. High volume will be driven by low-lead-count QFN and lead frame designs for power and other applications.
Source: Prismark Partners.