Much More Than Moore

News Analysis by Jeffrey C. Demmin, Advanced Packaging contributing editor

I must admit that the title of this was stolen from Carlo Cognetti of ST Microelectronics, who gave a very interesting keynote talk titled that at the Napa KGD workshop recently.

As usual, the Napa KGD Packaging & Test Workshop was a success, with many interesting talks plus a record attendance this year. (One hopes that the quality and popularity don’t make the event grow to the point that it changes that nature of it, but I’m sure that the organizers are on top of that challenge.)

The workshop started off with that keynote talk by ST Micro’s VP of New Packaging Development, Carlo Cognetti. Dr. Cognetti’s talk was titled “Much More than Moore” &#8212 he was quick to point out that he was referring to Gordon not Michael &#8212 and it had his take on what we can expect in the future of packaging.

The concept reflected in the title is that the progress of Moore’s Law, which is based on advances in integration and miniaturization at the silicon transistor level, can be surpassed by system-in-package technology. We have all heard (and many have participated in) the debate about system-on-chip vs. system-in-package, but it usually SoC that is cited as having better integration capabilities. According to Cognetti, there are two main ways that SiP does better than SoC for integration &#8212 with 3-D packaging and with the capability to integrate “almost anything.”

These are well-known advantages of SiP, but I hadn’t really thought of them as a way to beat Moore’s Law. Conventional density improvements in silicon, though, are stuck in the plane of the silicon wafer. There are certainly some intriguing developments in 3-D wafer processing, but nothing on that front approaches the mainstream usage of 3-D chip- and package-stacking. (Every cell phone today has some kind of stacked chips, for example.) Even if you aren’t using the latest silicon technology, you can still have higher functional density compared to the latest ICs by stacking two or more chips. It takes a lot of sweat in the wafer R&D lab to double the density of the silicon, but accomplishing that 100% increase by stacking a second chip on top is relatively easy these days.

Similarly, it is very difficult to integrate GaAs and silicon functions, for example, on one wafer. There are ways to do it, but the materials engineering and processing complexity are typically prohibitive. System-in-package technology does the job quite nicely, providing yet another capability that enables a leap past Moore’s Law.

Cognetti has plenty more to say, including some information about ST Micro’s packaging business. One interesting point was that while their volumes increased 3X from 1996 to 2003, their packaging headcount increased 50%, and their factor space increased only 20%. The output per person or per square meter obviously grew tremendously, which is an indication of the efficiencies that have been put in place there. I imagine that most IDMs (integrated device manufacturers) have seen similar trends.

Anyway, the quality and insights in Cognetti’s keynote talk did a nice job of kicking off another excellent Napa KGD workshop.

-Jeffrey C. Demmin, contributing editor


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