October 19, 2004 – Researchers at the Interuniversity MicroElectronics Center (IMEC) in Belgium have embarked on an ambitious system-level integration program that will explore circuit and system design concepts, addressing the growth of technology barriers as IC feature sizes are scaled smaller at the 45nm and below process nodes.

Unveiled at IMEC’s Annual Research Review Meeting earlier this month, the new program takes a cross-disciplinary approach to increasing the number of ICs that can pass power and performance specs while easing the manufacturing barriers. Rudy Lauwereins, VP of design technology for IMEC’s Integrated Information and Communication Systems, said that IMEC would first look for solutions at the circuit level and system level, where solutions may be cheaper” than at the technology level.

One such circuit-level “design-for-manufacturing” concept addresses power consumption in embedded SRAMs in data-dominated applications. To lower power consumption and deal with potential variations in SRAM transistor performance, IMEC has redesigned the buffers and control circuits around the embedded memory to include “control knobs” to measure transistor performance and, if needed, activate a series of buffers to ensure that low-power memory is performing as expected. The concept has been demonstrated in a DAB receiver design at the Spice model level, but not yet implemented in silicon. IMEC believes the concept could be applied to logic transistors as well.

IMEC research managers admitted that the concept represents a paradigm shift in design and manufacturing, and its use might not be embraced by the industry until device scaling problems reach the point where they threaten to significantly slow the pace of Moore’s Law or the launch of future process nodes. However, Lauwereins cautioned that the clock is ticking, illustrated by an increase in process variations as new technology nodes are introduced. “If [65nm CMOS] transistors are used to build a 1-kilobyte memory, you will end up with a 45% variation in memory access time and 40% variation of relative energy consumption. This is quite serious, even for moderate variations at the single transistor level…and it will get worse as we move to new technology nodes.” — J. Robert Lineback, Senior Technical Editor

For more coverage of IMEC’s efforts to address growing problems in device scaling, visit http://www.wafernews.com .