Novel Advanced Interconnects



Solder interconnects have been supplied for a number of years by captive manufacturers for PCs and for automotive applications. Contract wafer bump bonding manufacturers are providing reliable standard-pitch interconnects at low cost, while microelectronics materials suppliers continue to make leaping advances in the materials for these interconnect technologies. Advances in commercially available specialty materials for microelectronics have resulted in denser solder interconnects and more robust processes.

Demanding applications, such as high-performance imaging arrays requiring thinned wafers, may push the fine-pitch interconnect supply chain out of the processing comfort zone. Researchers at MCNC's Research and Devel-opment Institute (MCNC-RDI), a North Carolina-based nonprofit research organization, address these demanding requirements through the deployment of materials and novel designs to meet tomorrow's fine-pitch interconnection needs. This article reports on some novel fine-pitch solder interconnect solutions that resulted from the simultaneous deployment of these advanced materials, unique interconnect designs and assembly techniques.

Ultra-fine-pitch Flip Chip Interconnects and Novel Interconnects

Much has been written about standard flip chip technology. Recent technical conferences on flip chip technology were rife with reports on achieving finer pitch. Scientists working on high density pixel-array detectors appear to be leading the demand for these ultra-fine-pitch array interconnects (e.g., at Fermi National Labs and CERN).1

Although much has been written about the positive impact of increased pin counts and closer spacing of bumps on packaging of microelectronics, what lies beyond achievement of finer pitch? This article reviews unique examples where novel high-density packaging and interconnect of ICs are achieved through controlled design and manipulation of flip chip solder bumps and IC orientations. The work embodies a number of developments and patented technologies, and is the result of a cumulative effort of several individuals and project teams.

Requirement for Ultra-fine-pitch Pixel Detectors on Thinned Wafers. Photolithography processes and photoresist materials improvements have helped solve some of the limitations to achieving ultra-fine pitches for interconnection. Well-established processes exist, especially when vias are to be fabricated. For certain steps during processing, it is advantageous to attain smooth, sloping walls to ensure integrity of the conductive traces. Materials such as benzocyclobutene (BCB) provide a gentle, controlled and specific slope on which the metal traces are formed. The smooth slope is desirable for maintaining integrity at the base of the bump.2

Further up the bump stack, where columns of solder are to be plated, it is desirable to use a plating stencil that has a vertical sidewall angle, so that the top and base are practically the same size (Figure 1). This ensures that interconnections placed close to each other (fine pitch) do not encroach and short near the top because of a sloping sidewall. Such materials are constantly evaluated and potential impact on pitch size is considered.

Figure 1. This image shows a new plating photoresist material under evaluation.
Click here to enlarge image

For pixel-array detectors in medical imaging and particle physics applications, it often is desirable to minimize the silicon IC thickness. A challenge to the processing is wafer thinning after bumping. After the CMOS IC fabrication sequence, but before the bumping process, the wafers may be reliably thinned to 100 µm. Typically, however, wafer thinning is practiced only after the bumping process because there is significant damage risk to the thinned wafer during the 25 to 35 process steps. Also, thinned wafers may pose processing challenges during photolithography, because they tend to deflect and bow on a vacuum chuck, resulting in puddling of the wet photoresist and subsequent feature variations on the exposure tools. The thinned wafers may be processed through the bumping line by first temporarily bonding them to a carrier wafer with an appropriate adhesive. The primary risk associated with this approach is basically solvent attack on the adhesive layer during the bumping process. For solder plating in an acid bath, the adhesive layer may be severely attacked. This risk is reduced if a fountain plater or spray etcher is used. Carrier wafer bonding may also present the risk of nonplanarity between the carrier and device wafers.

Meanwhile, thinning after bumping poses significant risk as well. Currently, success is achieved only if the wafer bumped surfaces are properly protected with a temporary coat. New thick-resist formulations may prove to be more efficient, since only one coat is required to be thick enough to cover the bumps. Alternatively, it has been determined that waxes applied at the wafer-thinning factory to coat the bumps do not provide sufficient protection, resulting in missing and damaged bumps. Waxes also leave residues that hamper subsequent flip chip assembly and interconnection.

Requirement for Assembly of Flip Chips at Variable Heights. The advanced interconnect design idea of controlled variable height solder bump was offered as a packaging solution to a unique challenge. For this particular application, the peripheral pads on a particular optoelectronic device were 10 µm offset vertically from the central array of flip chip bonding pads, per the device design. To ensure consistent and reliable flip chip joining, the matching peripheral bumps were required to be fabricated approximately 10 µm taller than the central array of bumps. As Figure 2 illustrates, this was consistently achieved and resulted in a successful demonstration of the customer's high-data-rate optical package. The application of the novel interconnect approach is expected to provide solutions to unique packaging challenges in the future.

Figure 2. This image shows the controlled variable height solder bumps, for packaging of a high-data-rate optical system.
Click here to enlarge image

Requirement for Submerged Solder Bumps for Minimum Standoff Gap. Another challenging application required fabrication of solder bumps that were buried in a silicon “well” (Figure 3). To function according to the system design, the assembly of chip and substrate must have a controlled 4-µm standoff gap. This close gap of the pads-on-chip relative to pads-on-substrate is required to achieve capacitive coupling.3

Figure 3. Cross section of a chip/substrate assembly with buried bumps.
Click here to enlarge image

One difficulty in the fabrication lies in photolithography and patterning of reliable conductive traces in the well. It is well known that if improperly fabricated, conductor trace opens result from discontinuous coverage on the rim of the well. To overcome this, one approach being evaluated is the use of multilayering polymers to form the well. This yields smoother sidewalls that allow consistent coating of the sidewalls and rim of the well, thereby mitigating opens in conductor traces. The multilayering of polymer dielectric also offers an additional advantage, giving control of individual layer thicknesses between the metal layers, which circuit design engineers can exploit for this capacitive coupling application. Once the well is fabricated, the bumped IC can be aligned and joined to the substrate such that the bumps are recessed — yielding the desired 4-µm standoff between pads.

Requirement for Chip-on-edge Assembly for 3-D Density Packaging. Researchers used solder bumps proximate to the edge of the IC to achieve 3-D on-edge joining of chips. After precise fabrication of the bumps on the ICs and substrates, the chips were precision-aligned with custom prototyping chip- placement equipment. Final joining resulted during reflow of the mated solder bumps. The curved columnar joints resulted from the known high surface tension of molten solder. The novel 3-D interconnect concept is finding application in advanced packaging.4

Other Interconnect Technologies on the Horizon

The concept of 3-D interconnect technology is becoming increasingly important for applications where there is a demand for higher IC performance, as well as a reduction in package weight and volume. Researchers at MCNC-RDI are also developing high-density, low capacitance vertical through-wafer interconnect technologies. These interconnects enable 3-D integration of multiple layers of standard, commercially fabricated silicon ICs, or 3-D heterogeneous integration of multiple layers of silicon ICs with other ICs, 2-D sensor arrays, lasers or other semiconductor devices fabricated with dissimilar materials. MCNC-RDI has demonstrated vertical interconnects with diameters of 4 to 100 µm and high aspect ratios of up to 10:1. Because the resulting multilayer structures offer optimal short interconnect paths and enormous interlayer signal bandwidth, this approach to interconnect technology may herald the next phase in the evolution of advanced packaging.


Much emphasis is being placed on attaining finer-pitch interconnections. However, some novel advances presented here offer unique solutions to IC interconnect challenges.

Newly available commercial materials offer the required processing advantages to solve a host of limitations for fine-pitch interconnections. The materials of thick photoresists improve efficiency for solder bumping and wafer thinning by accomplishing the required thickness with only one coat. In addition, these resists offer a more vertical sidewall, thus allowing interconnects to be spaced closer together. Together, these improvements translate into fine-pitch interconnections at lower process costs. An approach to achieving the bumping of wafers thinned to 100 µm is being demonstrated. Secondly, design ideas for controlled variable height solder bumps, buried bumps and on-edge 3-D chip assembly have resulted in some unique solutions to advanced packaging interconnect challenges.


  1. K. Kwiatkowski, James C. Lyke, R. Wojnarski, C. Kapusta, “3-D Stacked Electronics Assembly for High Pixel Density Array Detectors,” presented at the Government Microcircuit Applications Conference (GOMAC), Tampa Florida, 2003.
  2. A. Huffman, R. LaBennett, S. Bonafede, C. Statler, “Eutectic Sn/Pb Fine-Pitch Solder Bumps and Assembly for Rad-Hard Pixel Detectors,” presented at the International Workshop on Semiconductor Pixel Detectors for Particles and X-Rays (Pixel 2002), Carmel, CA, Sept. 2002.
  3. Stephen Mick, Lei Luo, John Wilson, Paul Franzon, “Buried Solder Bump Connections for High-Density Capacitive Coupling,” presented at EPEP, July, 2002.
  4. G. Rinne, “Stacked Die using Flip Chip,” presented at Flip Chip Technology Workshop IMAPS, Austin, TX, June 2003.

RICHARD LABENNETT, principal engineer and manager of the Optical and Electronic Packaging Group, and ALAN HUFFMAN, researcher with the Optical and Electronic Packaging Group, may be contacted at MCNC-RDI, P.O. Box 13910, 3021 Cornwallis Road, Research Triangle Park, NC 27709; (919) 990-2000; e-mail: [email protected] and [email protected].


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