A PHYSICAL COMPARISON OF SINGLE- AND DUAL-GATE LOGIC
By FRANK MORTAN AND MATTHEW STOVALL
The demand for small, portable handheld electronic devices has led OEMs to reduce packaging sizes of all types and to create many choices to meet market demand. Regardless of function or pin count, size does matter — and the smaller the better. But how small is too small? Dual- and single-gate logic can come in either chip scale packages (CSP) or wafer scale packages (WSP), however, one or the other may be more practical for a particular application from a consumer product viewpoint due to overall size requirements or economics. New products can be designed to be smaller and better, but the cheaper part of the triad becomes difficult and requires careful cost benefit analysis to determine just how small is cost effective. Designers must analyze some of the important choices regarding board size, pad layout/pitch/trace width, and via or micro via (or none). Manufacturability and assembly yields also contribute to the overall success of the design. This article addresses physical comparisons for different packages, normalized costs for packaging, and factors influencing PCB technology costs, as well as assembly yields.
 Figure 1. 16-bit package area (mm2) over time. |
null
 Figure 2. Octal package area (mm2) over time. |
null
The Evolution of Logic
In the past, size requirements for logic packaging of all bit counts were of little concern. Processors and other high-end packaging were large by today's standards, leaving ample room for patching outputs. With the advent of the handheld electronics market, everything began to change for the smaller. 16-bit logic shrank approximately 72% in this time frame, octal packaging by 71% with respect to current CSP packaging, and by about 79% when compared to the newest quad flat no-lead (QFN, MO-241) packaging (Figures 1 and 2). Single-gate logic has progressed from the 5-pin SOT23 (JEDEC MO-178) to the SC70/SOT323, and further to a 5-pin VSSOP leaded package. The newest technology to compete with CSP and near-CSP packaging has evolved under MO-211, and is commonly referred to as wafer-level CSP. This bare-die bumped package has reduced single-gate logic sizes by 84% (Figure 3). Similarly, dual-gate logic has migrated from 8-pin TSSOP (MO-153) to 8-pin plastic small outline packages under MO-187, and eventually to wafer-level per MO-211 — a resounding 91% size reduction from the traditional package TSSOP, and an 88% reduction from the VSSOP packages (Figure 4).
 Figure 3. Single-gate package area (mm2) over time. |
null
Attribute Comparison of CSP vs. WSP
Wafer-level package parasitics are a great improvement over those of the CSP. In the case of TSSOP, VSSOP and SOT packages, wafer-level packaging offers lower parasitic inductance by eliminating the metal leadframe. In the case of CSP-BGA, the presence of trace lines in the BT or polyimide tape substrate causes parasitic capacitance levels to be higher than with WSP, which is usually a direct bump to pad attachment.
 Figure 4. Dual-gate package area (mm2) over time. |
Some wafer-level packages, if not originally designed as a WSP, require a redistribution layer (RDL) to make the connection from die to bump. This can add parasitic capacitance, but the RDL trace widths normally are narrower than the copper foil traces in CSP BGA substrates, which minimize adverse effects. The elimination of bond wires in WSP packaging results in very low parasitic resistance and inductance compared to wire-bonded CSP.
 Table 1. Modeled package parasitics of single-gate, dual-gate and 16/32-bit WSP and CSP packages. |
For single-gate logic packaging, package resistance, inductance and capacitance for WSP are respectively 96%, 98.6% and 70.5% lower than the SOT-23. When compared to SOT-323 package parasitics, WSP package L, R and C are respectively 95%, 97.9% and 68.5% lower. Table 1 shows package parasitics for various package alternatives of single gate (1G) and dual gate (2G). CSP-BGA is also shown to illustrate the potential reductions that could be possible when the next-generation WSP is developed for 16- and 32-bit packaging.
Thermal Performance
Many factors affect thermal performance, but PCB design is by far the most influential. Proper thermal management and board design can make either the CSP or WSP successful in a design, assuming the economic constraints of the product allow for proper thermal management. The number and weight of the metal layers in the PCB, the inclusion of ground or thermal vias, plus component placement/layout and proximity to other power sources, all have significant effects on dissipation (Tables 2 and 3).
 Table 2. Single-gate junction-to-ambient thermal resistance per JESD 51-7. |
null
 Table 3. Dual-gate junction-to-ambient thermal resistance per JESD 51-7. |
For the WSP, thermal performance is significantly improved by the fact that the package is a bare die, with no insulating effects by either mold compound or, as with the case of CSP-BGA, the tape or BT substrate. Both the WSP and the CSP-BGA have ball terminations, but the CSP-BGA generally has a higher thermal impedance from junction to board due to the thermal resistance offered by the die attach material, soldermask and substrate. Silicon transfers heat relatively well, having a thermal conductivity of approximately 1/3 that of copper, allowing better conduction through the die body of the WSP and into the balls, board and to ambient.
Relative Costs
The costs of using CSP or WSP packaging in a product design should be examined from two perspectives. First, and the easiest, is simple package cost. If costs are normalized to a common basis for single- and dual-gate packaging, we find the results shown in Tables 4 and 5.
 Table 4. Normalized costs for single gate. |
The second and most difficult issue to resolve is the cost of the required PCB design based on package choice. SOT, TSSOP, CSP-BGA and VSSOP packages require a lower level of complexity for PCB pad designs and board-level assembly. Leadframe-based CSP packages, however, also take up more total board space (package body plus leads), which is costly and may result in a product that does not meet size or weight requirements. WSP is much smaller and lighter, but requires a higher level of complexity with regard to PCB design.
 Table 5. Normalized costs for dual gate. |
Assembly yields of WSP involve a learning curve similar to BGA use, but have proven acceptable with <4-PPM defect levels. PCB costs also depend on the decision of how to use via or micro-via interconnects. The judicious use of well-placed vias is imperative to the overall cost. The under-utilization of via interconnects can result in a PCB design too large to meet size and weight requirements, whereas an over-utilization of via may allow miniaturization of a design, but drive costs to an unacceptable level. Overall product size requirements must be realistic, and the number of board layers and routing paths chosen wisely to minimize complicated layer interconnections.
Vias used for TSSOP, SOTs or VSSOP are cheaper to build, but may be offset by the area savings realized by the wise use of vias in conjunction with WSP or CSP BGA. Board-level producibility is well defined for CSP and CSP-BGA, but is still emerging for WSP array packaging. Currently, 60 to 70% of PCB fab shops are capable of producing WSP design PCBs, but at a cost premium. These costs may turn out to be worthwhile when the size reduction effect on overall cost is quantified. WSP pads generally range in size from 0.17- to 0.25-mm in diameter, depending on ball size, and will not allow for via in pad technology at this point in time due to PCB fab capabilities. Traditional dog-bone micro via or a standard via outside of the package outline, however, often take up less space than the older alternative packages.
The use of nonsoldermask-defined (NSMD) pads with CSP-BGA and WSP results in superior board-level reliability, as opposed to the use of soldermask-defined pads (SMD). NSMD allows for more solderable pad area (pad surface plus perimeter area) than the SMD pad definition. For packages mounted on SMD and NSMD pads of the same diameter, SMD packages fail approximately 35% earlier.
The diameter values for both types of pad definitions are usually given in the supplier literature and should be closely followed. Many WSP packages meet mounted temperature cycling requirements, as long as the ramp rates provide more of a temperature cycle profile vs. a shock profile (shock defined as >20°C/min. change rate). To prevent overkill in testing, observe IPC testing guidelines and adopt realistic temperature cycle requirements.
Underfill can greatly enhance the second-level reliability of both WSP and CSP BGA, and should be considered to meet physical/temperature shock or extended cyclic requirements. BGA-CSP first failures have shown slightly better performance than the WSP, with first failure between 1,500 to 1,800 cycles when tested at -40° to 125°C, 2 cycles/hr, and ramp rates that qualify as a shock (>20°C/min.). Leadframe-based CSP alternatives still show the best second-level reliability, but at a significant space consumption penalty.
Conclusion
WSPs offer significant area savings, improved package parasitics and power dissipation over leaded CSP and CSP-BGA packages. Simple package costs show an increase over baseline of 1.08 to 1.27X, but these costs can in many cases be more than recovered through smart board designs that use less laminate and allow the feasibility of new, smaller and more functional consumer goods.
MATTHEW STOVALL and FRANK MORTAN, packaging engineers, may be contacted at Texas Instruments, 6412 Highway 755, MS 812, Sherman, TX 75090; e-mail: [email protected] and [email protected].