Five years ago the promise of wafer-level processing for advanced packaging meant improved performance, reduced form factor, and the potential of reduced packaging costs. The initial reality was not up to expectations as advanced processes and equipment requirements and high-cost, complex substrates and underfill materials threatened to relegate the use of such technology to only those high-end applications that could absorb the cost in favor of the improved performance.
Recently, we have seen improvements in both manufacturing technology and capabilities, as well as a reduction in the cost of flip chip substrates and materials that, combined with the ever increasing need for performance, are driving the continued adoption of this technology into more applications. The impetus of these improvements has been the advanced packaging foundry sector, where improvements in both technical capabilities and manufacturing costs have led to double-digit growth in wafer-level processing technologies. Nowhere is this more true than in Asia, where the foundry sectors in Japan, Taiwan, China, and Singapore have become the dominant force in wafer bumping and wafer-level packaging manufacturing — exceeding the volume of the IDM sector.
The drive for improved “packaged” chip performance, and the drive for smaller form factors in the digital electronic sector, have created a new segment of “post passivation” wafer-level process technologies. These technologies are specifically focused on improving the performance of the packaged device and/or reducing the size and complexity of the end application, such as a wireless module. More importantly, these technologies take advantage of the existing wafer-level processing infrastructure in both the foundry and IDM sectors, and further bridge the gap between FOEL and BEOL manufacturing. They also have proven to be an excellent means of providing additional value in the wafer-level processing market for the foundry sector.
These post-passivation technologies, including high-speed or high-power transmission lines, on-chip integrated passive components, and stress buffer layers, are enablers for both true wafer-level packages and for system-in-package applications. On-chip integrated passive components combined with high-speed transmission lines are enabling drastically reduced form factors and improved speed and power performance for wireless modules. The use of post-passivation, high-speed transmission lines can greatly improve thermal and electrical performance and, combined with ground plane layers, can enable drastically improved signal performance. The introduction of photo-definable stress buffer materials at the 65-nm and below technology nodes will assist in mitigating stress-related failures induced by the use of low-k dielectric materials, combined with the high CTE mismatch created by the use of today's low-cost organic substrates.
While most of these post-passivation technologies are not new, the development of manufacturing capable processes are. The maturation of these technologies into mainstream manufacturing is similar to that of solder bumping or wafer-level chip scale packaging, where the IDMs led the way, but also encouraged the outsourcing model from their foundry partners. The good news is that most of the infrastructure already exists at packaging foundries, and the experience in using the more sophisticated wafer-level processing equipment already is in place. The challenges in implementing these post-passivation processes in foundries will come from new materials and equipment requirements brought about by the need for high-aspect-ratio, plated-copper structures, and polyimide-based insulating materials, and the necessity for finer, tighter-pitch geometries. Fortunately, as these technologies gain wider acceptance with IDMs, the need for outsourcing will become greater and the transfer of these technologies will become inevitable.
The use of wafer-level processing technologies to enable improved packaged device performance is continuing to gain acceptance. The functionality provided by the addition of post-passivation process technologies into these wafer-level processes is providing additional value and capability for today's demanding digital electronic components. The improved functionality and performance that wafer-level processing provides, combined with the continued industry acceptance of these technologies as mainstream alternatives to conventional packaging, is proof that the future of wafer-level processing for advanced packaging applications continues to be a bright one!
 |
STEPHEN KAY, director of Marketing for Advanced Packaging Technology, may be contacted at Ultratech Inc., 3050 Zanker Road, San Jose, CA 95134; e-mail: [email protected].