Chipmakers speed up strained-Si process

Dec. 13, 2004 — Researchers from IBM and AMD, with help from Sony and Toshiba, have developed a strained silicon technology that improves transistor speeds by up to 24% at given power levels.

The “dual stress liner” technique can be integrated into volume manufacturing using standard tools and materials, without requiring new production techniques, and also works with silicon-on-insulator technology. It was developed at IBM’s Semiconductor Research and Development Center (SRDC) in East Fishkill, NY, and at AMD’s Fab 30 facility in Dresden, Germany.

Both IBM and AMD plan to integrate the new strained silicon technology into their 90nm processor platforms–including AMD64 multicore processors and IBM’s Power Architecture-based chips–with shipments slated for 1H05.

“Innovation has surpassed scaling as the primary driver of semiconductor technology performance improvements,” said Lisa Su, VP of technology development and alliances, IBM Systems & Technology Group. This new co-developed process “demonstrates that companies willing to share their expertise and skills can find new ways to overcome roadblocks and help lead the industry to the next generation of technology advancements.”

The companies will disclose more details of the “dual stress liner” process this week at the IEEE International Electron Devices conference in San Francisco, CA.


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