Full Wafer Contact Technology: A KGD Enabler



The average person will encounter more than 300 embedded processors every day by 2010, according to Semico Research. Business Week magazine reports that in the next 5 years, practically every machine and gadget that sings, talks, beams images or messages will sport a powerful computer and network connection. The demand for highly reliable, embedded semiconductor solutions is growing at 8 to 10% per year for automotive applications alone, according to Strategy Analysts, putting production of known good die (KGD) at the forefront of the demand spectrum.

Figure 1. Expanded automotive applications.
Click here to enlarge image

A full wafer contact technology* has been developed to enable KGD microcontrollers for the automotive industry, for use in everything from transmission and engine controls to smart connectors and wireless brake and steering controls (Figure 1). Today, there are only a few processes that can deliver true KGD. Statistical good die selection, test methods like HVST and IDDQ, burn-in via individual die carriers, and sacrificial metal wafer-level burn-in processes commonly are used. However, these processes are nearing the limits of their technology, screening effectiveness, and cost effectiveness. A next-generation process of directly contacting the full wafer has been developed to extend the existing technology's boundaries. This article compares these various processes, their strengths and weaknesses, and defines a roadmap to achieving KGD.

KGD Processes

Processes for producing KGD are varied, depending on the targeted quality levels, process defectivity (natural wafer yields), I/O pad pitch, volumes, device type, and initial cost of implementation. For most mature technologies with less stringent quality requirements and high natural yield, the best option is to process without burn-in. However, supplying zero-defect, highly reliable KGD typically requires some level of extended temperature stress testing.

The least expensive path to achieving KGD usually is a non-burn-in process. A typical KGD process flow is shown in Figure 2. For “good enough” die, the non-burn-in flow is adequate; however, burn-in generally is required to achieve lower defect levels. Considerable effort is placed on HVST/IDDQ testing to produce highly reliable KGD, but success is dependent on the device configuration and defect density.

Figure 2. Typical KGD with flash. Left flow is without burn-in, typically flash-only devices. Right flow is with burn-in, generally for microcontrollers with embedded flash.
Click here to enlarge image

Generally, new products initially have some level of burn-in to screen out latent defects. As fabrication processes mature and the defectivity level is improved, burn-in reduction and subsequent elimination can be realized. From Murphy's yield model, it is evident that process defect density has a direct effect on natural yields. For the most highly reliable KGD products, absolute burn-in elimination rarely is successful, because only the absolute lowest defect density processes would be eligible. For normal processes with lower reliability requirements, the product can be produced without burn-in. For highly reliable KGD, however, some level of burn-in usually is a necessity.

Die Burn-in Processes

Once the decision is made to adopt the burn-in flow, the question is which method to use. The answer to this question is complex, requiring considerable cost and trade-off analysis, in which some of the first order inputs are unknown at the early stage. The three possible technologies to burn-in die are: individual die carrier, sacrificial metal WLBI, and direct- contact WLBI. Table 1 lists these three methods and their attributes. With coarser-pitch devices, it is possible to reduce the initial investment by adopting the carrier method. But, as volumes are ramped, the higher parallelism of WLBI methods offer cost advantages. In either case, as pitch requirements shrink <120 µm, the carrier and sacrificial metal processes run into technology limits.

Table 1. Three methods of die burn-in. Note the pitch limitations of existing carrier and sacrificial metal WLBI.
Click here to enlarge image

Carrier Method. The carrier method uses a socket carrier that mounted to the individual die. The carrier is a reusable temporary package that enables burn-in and test as an oversized package. The mounting process requires alignment of the die pads/bumps to the carrier contacts. Manually, this is a slow, manpower-intensive process, not suitable for high-volume manufacturing. Alternately, automated pick-and-place equipment exists that can vision-align the pads to the carrier contacts. Although faster than manual placement, this still is relatively slow compared to full wafer batch processing. In addition, as the pad pitch shrink <120 µm, this method faces exponential difficulty because of the required alignment accuracy and availability of a suitable carrier contactor. Since package burn-in infrastructure is well established with most manufacturers, using carriers to fit within existing equipment sets offers some process and tooling efficiency for burn-in at the die level.

Sacrificial Metal Method. The sacrificial metal method places a metal interconnect layer tying common pins and routes them to interface pads. The dice are electrically grouped into clusters, share power, and drive signals in common. The electrical contact with the wafer is made through pogo pins to the burn-in system. Upon completion of the burn-in cycle, the metal layer is stripped off — isolating the individual die for subsequent probe. In the event of a short, the entire cluster is shut down; thus, not burned-in. This results in potential yield loss.

Until recently, the sacrificial metal layer process was the most common method of full wafer burn-in. Metal plating routing requirements and today's compact die designs, however, require a different approach. The process complexity is compounded with some advanced wafer fabrication process, because of increased sensitivity to the deposition and removal of metal layers. For some high-volume applications, with access to plating and metal etching processes, the highly parallel processing of sacrificial metal can be a viable way of bare die burn-in.

Direct Contact Method. The direct contact WLBI method incorporates the simplicity of the probe process on a full wafer to take advantage of massive parallelism. Effectively, it is the implementation of a full wafer contactor that interfaces every pin independently to the burn-in system. The contact technology contains three components: high-density circuit board (ICB), Z-compliant contactor, and bump membrane. Alignment between the contactor and die pads is achieved with a modified prober, and force is applied by vacuum. It is capable of <100-µm contact pitch and other contactor technologies such as nano and variations of MEMS technologies are capable of <50-µm pad pitches. In all cases, because of its simplicity, the direct contact process allows for interchangeable components.

The contactor is designed to accommodate the planarity variations between the wafer and ICB, while holding contact resistance to less than 1 Ω. This is achieved by Z-axis conductive particles that make electrical contact upon compression. As the wafer is subjected to temperature extremes, it is designed for CTE as the wafer, contactor, and ICB expand at the same rate. The ICB is laminated to a ceramic core, the compliant contactor is built onto a metal frame, and the membrane also is mounted onto a ceramic ring.


From a technical perspective, the direct contact method is capable and superior to other known methods. More importantly, these characteristics are scalable to accommodate finer pitches. However, these capabilities come at high initial investment costs.

Unlike traditional burn-in sockets, there is little infrastructure to support multiple contactor vendors to drive down component costs. Currently, each of the three components are designed and manufactured by different vendors. Each product introduction involves three separate suppliers, NREs, and supply chains. A comparison of fixed and variable costs between sacrificial metal and direct contact wafer-level burn-in can suggest opportunities for cost reduction. Because of the consumable materials and costs of plating processes, the variable cost of sacrificial metal processing is the most significant component of the cost to process a wafer. Variations in volume of product do not affect this cost component that is applicable on a per wafer basis. Fixed costs for the sacrificial metal are a significantly lower, due to the low cost of tooling and equipment. Conversely, the direct contact process requires significant fixed cost, due to the high cost of specialized wafer contactors and test equipment (Figure 3). The comparison in Figure 3 highlights the largest opportunity of cost reduction for each process. The belief is that the direct contact process has the most achievable opportunity to reduce cost of its relatively new contactor and test technologies, while sacrificial metal has less opportunity to reduce the costs of well-established plating and metal removal processes.

Figure 3. Cost components of direct contact and sacrificial metal WLBT processes.
Click here to enlarge image

Of the three methods to burn-in bare die, each, only the direct contact method offers a solution that can meet the requirements of the next-generation, finer-pitch KGD products. Due to the high contactor and equipment development costs, however, this process faces significant barriers to becoming a standard methodology — until integrated solutions are developed to reduce the fixed-cost component. This may happen when end customers demand highly reliable, fine-pitch KGDs from IC manufacturers, who must invest in direct contact WLBI. As demand for WLBI contactors and equipment is generated, suppliers will enter the market and offer lower-cost, integrated solutions.


  1. Ivy, Wilburn L. et al., “Sacrificial Metal Wafer Level Burn-in KGD,” 2000 Electronic Components and Technology Conference.
  2. Beddingfield, Craig et al., “Wafer-level KGD for DCA Applications,” Advanced Packaging, September, 1999.
  3. Cooper, Tim et al., “Demonstration and Deployment of a Test Cost Reduction Strategy Using Design-for-Test (DFT) and Wafer-Level Burn-In & Test,” Future Fab Intl., July 2001.
  4. Hazlett, Les et al., “Wafer-Level Burn-in Development at Motorola,” Nikkei Microdevices, February 1999.
  5. Nakata, Yoshiro et al., “A Wafer-Level Burn-in Technology Using the Contactor Controlled Thermal Expansion,” 1997 International Conference on Multichip Modules.

*By Freescale Semiconductor Inc.

JOHN PITTS, technology development manager, Final Manufacturing Technology Center, may be contacted at Freescale Semiconductor Inc., 6501 William Cannon Drive West, Austin, TX 78735-8598; e-mail: [email protected].


Easily post a comment below using your Linkedin, Twitter, Google or Facebook account. Comments won't automatically be posted to your social media accounts unless you select to share.