By Dr. Paula Doe, Contributing Editor

After all these years of hype, vertical interconnects are finally starting to replace horizontal connections in real products. Infineon is directly connecting security controller chips on top of memory chips in smart cards. Mattel’s new Juice Box media player for kids uses Matrix Semiconductor’s built up layers of programmable ROM for its videos on memory cards. And Tezzaron Semiconductor is now testing and qualifying its bonded memory-processor and memory chip stacks for first shipments to customers for evaluation.

“There are a lot of dead bodies on the road,” admitted Robert Patti, CTO of Tezzaron in Naperville, IL, of the past history of 3D interconnect. “Up until about a year ago when Bernie Meyerson at IBM said scaling was at a dead end, people didn’t believe it. But the people who’ve stuck their finger into the 90nm world have discovered it’s a really ugly world, and that changes the way people think about the next generation. Now 3D looks interesting.”

While the longer-term potential for increasing speed by using shorter interconnects is perceived to be in high performance devices, the actual vertically-interconnected chips out so far are in fact for low-cost consumer products, and derive as much from evolution in packaging and LCD technology as from revolution in standard CMOS design.

Infineon claims its direct face-to-face copper-to-copper bonding of chips allows higher density, higher speeds, and smaller footprint than SiPs, with lower cost and more flexibility than SoCs. It appears this ideal is now possible in large part thanks to recent major strides assembly toolmakers have made in handling ultrathin die, and placing and bonding them with increasingly high speed and accuracy. The chipmaker worked with Datacon, Radfeld, Austria, and EV Group, Scharding, Austria, to develop the equipment for the process.

Infineon first coats the wafer surfaces, and can reroute the bond pads, with a planar film of copper and tin, patterned to remain on the contact points, which allows higher interconnect density than bumping. A Datacon flip-chip bonder with a very large turbo range places known good die one by one only on the marked good die scattered across the 300mm base wafer, with alignment accuracy of 10 micron (3 sigma), then attaches them with a temporary polymer adhesive, all at an effective rate of about 4000 units/hr, depending on how many good die there are. An EVG wafer bonder then applies 270 degrees C heat and pressure for one to two hours to permanently bond the chips. With Infineon’s solid liquid interdiffusion technology, the copper-tin forms a eutectic alloy that can then resist heat up to 600 degrees C, so other chips could be added on top of the first bonded pair with the same process.

“The hard part is maintaining alignment of the chips during bonding,” explained Paul Lindner, EVG CTO, of his company’s part. “We have to make sure the chips expand with the wafer and stay in place, by controlling where we introduce the force and using a compliant layer.” A software connection from the Datacon tool tells the EVG bonder how many chips are attached where for each individual wafer, so it can adjust the direction of the down force on the pressure head appropriately to distribute the load uniformly across the wafer, so every chip gets the same contact force. Lindner said they maintain alignment within 5 micron through the bonding.

Ziptronix, Morrisville, NC, similarly is now also using a Datacon assembly tool to place individual known good die on a base wafer for its 3D chips. A spokesperson said the company expects to make an announcement about first silicon in the first quarter, for a 3D SoC that integrates flash, DRAM and FPGA technology in one device for better performance at lower cost.

Ziptronix physically attaches the chips with its own dielectric-to-dielectric covalent bonding technology, where the surface-treated parts bond directly on contact at room temperature without need for a separate bonding tool. Then it has to make the electrical connections, grinding down the top bonded die from the back to expose its circuits, then connecting these circuits either over the edge or through a via to the chip underneath. The company says it’s a simple, five-mask process to expose the bonding points on both die and connect them. It argues that using no heat in the bonding avoids introducing stress that can warp the wafer, especially at 90nm and beyond.

Tezzaron, the only one of the 3D interconnect upstarts to come at the problem from the design side, is apparently also the only one taking what once seemed the more conventional approach of bonding wafers to wafers and connecting them with deep vias, and aiming these more integrated devices at high performance niches.

“We’re circuit designers,” pointed out CTO Patti, noting Tezzaron’s ASICs background. “The rest are process people. The problem with 3D is how to use it.” He noted that others have had bonding that works, but the designers didn’t know what to do with it.

Patti said with that with silicon now in hand Tezzaron should have customer reliability and performance data by the end of 1Q05, aiming at prototype DRAMS in a year, ramping to production in five quarters, and prototype stacked SRAMs by 3Q05, with volume production in 4Q05. He argued the short vertical interconnects will allow two to eight times the speed, at lower cost, for high-speed memory applications.

The company takes wafers finished up to the last dielectric layer, then at its fab in Singapore adds deep vias and copper interconnects, then bonds the wafers face to face with copper thermal diffusion bonding at 350-400 degrees C, using an EVG bonder with alignment accuracy of 0.3 micron (3 sigma). Patti said they trick Cadence design tools into thinking the 3D connection design is 2D, so they can use Cadence tools along with some they developed on their own to place and route in 3D, though they are also now doing some co-development with Cadence for improvement.

The vias were originally 2-3 micron wide and 8-10 micron deep, but a new process that requires a little more processing from the foundry now has them down to 1.2 micron wide. The back of the top wafer can then be ground, polished and etched down to a thinness of about 3 micron, down to the copper studs, then oxide insulation built up and more copper circuits made, for bonding to the face of a third wafer, and the process repeated as desired. Cost of the stack with its two mask steps for the copper layer and via interconnect should be about $120/layer in volumes of 10,000 wafers.

“We couldn’t do this until copper became widely available,” added Patti. “Aluminum is unworkable for bonding, but copper is ideal. And we had some good dumb luck with certain things in the process you have to do to get it to work.”

Yields of wafer-to-wafer bonding could be a problem, with one bad chip wiping out a whole column stack. “Our philosophy is that stuff is going to fail,” said Patti. ” So we design for repair and redundancy.” Since the 3D architecture allows lots of connections without slowing performance, the chips include circuits for remapping around defects.

“Wire delay has become the problem,” asserted Patti. “There’s no real solution. If they can find a low-k material for 65nm that has Keff in the upper twos, then the circuits might run as fast as 90nm devices. But the only way to get to 10GHz will be to make the wires shorter.”

While breakthrough assembly equipment enables the bonded wafer or chip-to-wafer 3D interconnect development at Infineon, Ziptronix, and Terrazon, the 3D memory now shipping in volume from Matrix Semiconductor, Santa Clara, CA, owes more to polysilicon TFT LCD technology. And in Japan, startup ZyCube has a bonded wafer approach of its own.

Matrix’s process starts with a conventional CMOS base with a couple of levels of interconnect, then builds up multiple layers of memory cells of vertical polysilicon diode posts, alternating with tungsten interconnects. An SiO2 antifuse film separates the top of each diode from the interconnect. When enough biasing voltage is applied, the antifuse breaks down, connecting the diode to the tungsten, permanently programming the memory.

The company is offering a 64-megabit multimedia ROM card for $9.00 in quantities of 100 — significantly less (~40%) than the cost of flash memory — and says it has shipped 1 million units in the last four months, made by standard processes at TSMC and Amkor. The company aims this stacked programmable memory at providers of content for low-cost mobile devices, offering programming in days compared to months for a conventional mask ROM. The bulk of its production volume has now moved from 0.25 micron to the 0.15 micron design rule.

“There’s no way anyone can reproduce the electron mobility of an organized crystalline structure in polysilicon,” explained Matrix COO Siva Sivaram. “But the objective here is not high speed RAM. The aim is more like the human experience, for high throughput, high volume information. Any single access time is not fast, but there are many points. It is comparable in speed to NAND Flash.” He says that rapid thermal anneal in the 500 to 700 degree C range of the deposited amorphous silicon crystallizes it into large enough crystals for reasonable performance.

The company used fab facilities at Cypress Semiconductor to develop the process, then did the tough integration work at TSMC, using standard tools and materials in somewhat new ways. They had to figure out how to use the standard CVD tungsten process not for plugs, for example, but for the main interconnect lines, with associated problems with stresses and adhesion and the like. “First we had to convince the foundry that this startup would load enough wafers to be worth their trouble to work on this,” said Sivaram, “But they liked the idea of making consumables that were sold to end customers, that might be less cyclical and help with fab loading.”

Building the devices uses lots and lots of CMP, and standard subtractive tungsten, “old fashioned print ’em and etch ’em,” noted Sivaram. The polysilicon is doped in situ. Having to print only lines and posts allows the company to optimize phase shift masks to push lithography to do the 0.15 micron process with 0.3 micron pitch. Figuring out how to test all the burn-once antifuses presented another problem. The chip includes test elements, and enough extra circuits for onboard error checking and remapping around problems. — P.D.