By J. Robert Lineback, Senior Technical Editor

Researchers at the Interuniversity MicroElectronics Center (IMEC) in Belgium have embarked on an ambitious program to change the meaning of “design for manufacturing.” During IMEC’s Annual Research Review Meeting this fall, managers outlined a new system-level integration program that will explore circuit and system design concepts, addressing the growth of technology barriers as IC feature sizes are scaled smaller at the 45nm and below process nodes.

“In the past, traditional scaling always solved power problems, increased speed, and brought about cost savings, but beyond 100nm, we are beginning to see more problems emerge and fewer benefits,” explained Rudy Lauwereins, VP of design technology for IMEC’s Integrated Information and Communication Systems, at IMEC’s headquarters in Leuven, near Brussels. Topping the list of growing problems in device scaling are: mismatched transistor performance, gate leakage, increased resistivity in smaller copper interconnect lines due to electron scattering, and unpredictable performance over time and temperature ranges.

These problems and others will result from manufacturing tolerances in next-generation process technologies not scaling at the same pace as the physical gate length of transistors, said Lauwereins. Consequentially, IMEC has decided to pull together a new program that takes a cross-disciplinary approach to increasing the number of ICs that can pass power and performance specs while easing the manufacturing barriers. “It will be difficult, if not impossible, to find solutions only at the technology level,” Lauwereins cautioned. “It will be very expensive [to address power and performance issues] at the technology level. In that case, we should start looking at the circuit level and system level, where solutions may be cheaper.”

One such circuit-level “design-for-manufacturing” concept that’s being tried by IMEC addresses power consumption in embedded SRAMs in data-dominated applications. “In digital audio broadcast [DAB] applications, random-access memory accounts for two-thirds of the power consumption, while program memory and address/control circuits accounts for another 20%,” Lauwereins said.

To lower power consumption and deal with potential variations in SRAM transistor performance, IMEC has redesigned the buffers and control circuits around the embedded memory to include “control knobs.” These circuits will measure transistor performance and, if needed, activate a series of buffers to ensure that low-power memory is performing as expected. IMEC managers described the design as “cheap Pareto config knobs.” Since the additional buffers and controllers are designed into the memory peripheral circuits, the increase in die size is minimal.

“We can cope with dynamic and static process variability,” said Lauwereins, referring to performance drift over time and temperature as well as transistor yields from wafer processes.

“Process variation is increasing. It is worse that you might expect,” said the IMEC manager, referring to plot showing a “moderate” variation of ±10% threshold voltage in 65nm CMOS transistors. “This sounds reasonable, but it these transistors are used to build a 1-kilobyte memory, you will end up with a 45% variation in memory access time and 40% variation of relative energy consumption. This is quite serious, even for moderate variations at the single transistor level, and it will get worse as we move to new technology nodes,” Lauwereins warned.

The new “knobs” designed into embedded memory will automatically create tradeoffs to stabilize the function of the circuit block. The concept would enable 100% wafer yield of embedded SRAM circuits at 45nm and beyond as well as system-level reliability over time and temperature, if design automation suppliers and device manufacturers embrace the approach, suggested Lauwereins. The concept has been demonstrated in a DAB receiver design at the Spice model level, but not yet implemented in silicon. IMEC believes the concept could be applied to logic transistors as well.

IMEC research managers admitted that the concept represents a paradigm shift in design and manufacturing, and its use might not be embraced by the industry until device scaling problems reach the point where they threaten to significantly slow the pace of Moore’s Law or the launch of future process nodes. “This could be sometime after the 45nm node, but we must begin to look for solutions now,” Lauwereins told Solid State Technology after IMEC’s review. — J.R.L.