J. Robert Lineback, Senior Technical Editor

The next big step for development of 193nm immersion lithography will be fully equipped R&D pilot lines, expected to be operational in early 2005. These pilot lines will define immersion-related defectivity issues in functioning devices. Already, though, preliminary results from a couple of “split-lot” experiments in 2004 indicate no major problems lie ahead, and that mixing the use of new immersion tools and conventional dry scanner processes may be relatively simple.

In December 2004, chipmaking rivals IBM Corp. and Taiwan Semiconductor Manufacturing Co. Ltd. separately reported success in using the same immersion prototype scanner from ASML Holding NV to expose one mask layer in functional 90nm ICs. IBM used a split-lot approach to compare 193nm ArF scanner exposures–wet and dry–for an interconnect layer in 64-bit Power processors. Silicon foundry giant TSMC said it also performed a split-lot test using the same ASML TwinScan AT:1150i immersion scanner, to expose a polysilicon layer in the transistor gate stack of working 90nm devices.

IBM used the ASML 1150i (0.75NA) scanner in the October/November timeframe after the prototype tool was installed at the Albany NanoTech center in Albany, NY. TSMC, meanwhile, said it had sent wafers to ASML in the Netherlands for exposure of the poly layer prior to the 1150i being shipped to Albany. In both tests, IBM and TSMC completed wafer processing using dry lithography tools in their own fabs.

In a presentation at Cymer Inc.’s Lithography Symposium at Semicon Japan on Dec. 1 – one day before IBM disclosed its immersion tests during a briefing in China – TSMC disclosed preliminary results from its front end of line (FEOL) immersion-vs.-dry exposure tests. TSMC said those tests were conducted with the same 90nm resist and etch recipe, which acted as a baseline to uncover hidden risks in immersion processes.

“While some optimization may still be in order, we have promising results pointing to immersion lithography systems and tools capable of producing functional deep-submicron devices that will scale well below the 90nm node,” stated Burn Lin, senior director of TSMC’s micropatterning division in Hsinchu, Taiwan. “The larger focal range is the most significant finding, because it suggests that immersion tools can safely image with better yield than previously anticipated. This finding can be extrapolated to infer even greater benefits at the 65nm node.”

Like IBM’s experiment in the back end of line (BEOL) interconnect layer, TSMC’s FEOL exposure showed yield, device characteristics, and defect levels were comparable for both dry and wet scanners. TSMC has begun the installation of ASML’s new XT:1250i (0.85NA) immersion scanner to expand development and process evaluations in 2005.

Also finishing installation of an ASML 1250i 193nm ArF system is the Interuniversity MicroElectronics Center (IMEC) in Belgium, which will explore immersion lithography’s ability to greatly improve depth-of-focus (DOF) compared to dry 193nm scanners. IMEC and ASML have reported that early results from the 1250i scanner–prior to its delivery–showed a DOF of 0.7}mum, 1.7