By M. David Levenson, Senior Editor, Lithography
Will an industry that expects optical exposure tools to print more than 100 300mm wafers/hour embrace $20 million lithography systems with throughputs below 5 wafers/hour if they don’t require costly masks? If so, at what node? These were two of the questions that 110 participants tried to answer at the first Sematech Maskless Lithography (ML2) workshop, held January 17-19 in San Jose, CA.
Proposed ML2 tools come in two flavors: optical and charged-particle beam, and they promise to improve the economics of short production run devices, or extend the roadmap beyond the ultimate capability of 193nm immersion lithography, or both. Showcasing the efforts of Europe’s MEDEA+, Japan’s ASET, and other consortia, as well as the US’ NIST ATP and DARPA programs, the ML2 workshop included oral presentations about four e-beam concepts and one optical tool, and 13 papers presented other approaches to ML2 production. The workshop concluded with Sematech’s familiar prioritization of unresolved issues.
At one time, the quicker turnaround time (and time-to-market) of flexible maskless production more than made up for the lower throughput, but as Moore’s Law advanced, the need to print more and more pixels overwhelmed technical advances in shot frequency, according to Hans Pfeiffer of HCP Consulting. What had been a 22 wafers/hour technology became a 12 hour/wafer inconvenience. Tools being developed today employ parallel architectures as well as fast CMOS, optics, and MEMS technologies to approach 5 wafers/hour, but a gap remains between the research demonstrations and practical production.
Meet the contenders
While the ASML/Micronic Laser Systems optical ML2–based on ASML’s Twinscan platform and the spatial light modulators (SLMs) used in Micronic’s Sigma-7300 mask pattern generator–is most similar to today’s technologies, the majority of the schemes discussed at ML2 involved electron beam lithography. Thus, according to Daniel Henry of STMicroelectronics, they must overcome the fabs’ unfamiliarity with e-beam production technology as well as real technical problems. Still, direct-write e-beam lithography is used to fabricate some wafers today.
Akio Yamada of Advantest presented a multicolumn cell (MCC) character projection (CP) e-beam lithography system based upon the well-established Advantest F5113 single-column CP platform. Character projection assembles chip images from 60-100 2 micron square stencil patterns, selected by the electron beam. With proper stencils the first generation 16-column Advantest MCC/CP system should achieve 10 wafers/hour in 2008 — in time for the 45nm node. At low wafer volume, such a tool would have the lowest cost of production, according to Yamada.
Leica and IMS are collaborating on a single-column PML2 machine that avoids Coulomb-interaction blur at high throughput through large demagnification. Christoph Brandstatter described a system with 290,000 individually-blanked 100 kV electron beams, each 25nm in dimension and running at 1MHz. Redundancy in the aperture plate would allow each wafer pixel to be written 64 times, producing 64 gray levels with a 25Gb/sec datapath, comparable to today’s leading communications technology. Proof of 45nm lithography capability is scheduled for 2006, with a production machine available by late 2008.
Bert Jan Kampherbeek of MAPPER, a 30-person Netherlands startup, described a lower voltage system where the 13,000 electron beams are switched at 250MHz by an equal number of optical fibers. Rather than using a single lens for the entire array, each of the MAPPER beams is focused individually to avoid the Coulomb blur — essentially a 13,000 column system. Already 30nm half-pitch lines and dots have been fabricated with a 25 beam prototype, but the first tool (contemplated for delivery in early 2007) will only be capable of 1 wafer/hour throughput. Higher throughput will require even more beams and columns.
The sole presenting US company, Multibeam Systems Inc., plans to use a “vector-shaped multibeam” architecture to print 45nm CDs at 5 wafers/hour in 2007. The 10 beams will be rectangular, spaced at 30mm intervals and, with one per column and no crossovers to cause blur, should achieve an edge-placement accuracy of 1nm. The relative simplicity of this design may give it a cost advantage.
The ASML/Micronic optical ML2 program is presently funded by DARPA for low-volume insertion near the 65nm node. The SLM technology is now being explored at the Wilton, CT facility. Both resolution and throughput remain issues for this system, which can be updated only at the 4kHz pulse rate of an excimer laser. Thus many, many pixels must be flashed together. Micronic’s Sigma-7300 mask pattern generator, which uses one 1Megapixel tilt-mirror SLM, requires three hours to write one 6-in. mask plate at 150nm resolution.
Promises and challenges
While proponents of maskless lithography want to avoid the costs and difficulties of critical-level optical lithography, they do not agree on a single candidate replacement, or even on the key virtues that such a new technology should have. Masks, for all their faults, hold tremendous volumes of data that can be verified in their entirety before being transferred. Developing methods to verify the correctness of wafer patterns actually being printed on multibeam maskless tools constitutes the top technical challenge, according to the workshop participants. Other challenges include stitching, avoiding contamination (and consequent image instabilities), achieving adequate throughput, and having a tool available when needed for insertion at the 45nm node (or 32nm or 22nm).
Maskless lithography may be most economical in small-volume niche applications, but those niche fabs cannot support the ML2 R&D effort by themselves. To attract the sponsorship needed to succeed, the ML2 technology will have to drive towards some unique large-volume application, extending the Roadmap beyond the nodes accessible to 193nm immersion lithography.