March 22, 2005 – Industry leaders, working through the Silicon Design Chain Initiative, today announced new, silicon-validated, low-power design techniques to achieve total power savings of over 40% on a 90nm test design.
In close collaboration, members of the initiative, including Applied Materials, ARM, Artisan Components, now part of ARM, Cadence, and TSMC, have developed an integrated power management methodology that optimizes SoC power and performance, with minimal disruption to existing RTL flows.
This simplified approach combines design implementation tools such as Cadence Encounter digital IC design platform, Encounter RTL Compiler synthesis, Encounter CeltIC NDC (Nanometer Delay Calculator) signal integrity analysis and VoltageStorm power analysis, with ARM’s Artisan standard cell libraries and memories, including support for the Cadence effective current source model (ECSM) format through lib_ecsm library views for standard cells.
“Power consumption is one of the major issues facing our industry as we move to the 90nm technology node and beyond,” said Mike Smayling, CTO of the Maydan Technology Center at Applied Materials. “We are excited by the work done by our fellow members of the Silicon Design Chain in developing this important low-power design solution, and will continue to support these critical projects by providing the process and inspection technologies needed to enable these advanced chip designs.”
“This is the first time industry leaders have banded together to correlate real power savings into real silicon, which should dramatically increase the adoption rate for 90nm technology,” said Edward Wan, senior director of design service marketing at TSMC. “This project exemplifies the power of strategic collaboration to significantly differentiate our respective technology offerings.”