NIST unveils atom-based standards for measuring chip features under 50nm

March 1, 2005 – Device features on chips as small as 40nm wide can now be measured reliably thanks to new test structures developed by a team of physicists, engineers, and statisticians at the Commerce Department’s National Institute of Standards and Technology (NIST), SEMATECH, and other collaborators. The test structures are replicated on reference materials that will allow better calibration of tools that monitor the manufacturing of microprocessors and similar integrated circuits.

NIST says the new test structures are the culmination of its more than four-year effort to provide standard “rulers” for measuring the narrowest linear features that can be controllably etched into a chip. The NIST rulers are precisely etched lines of crystalline silicon ranging in width from 40nm to 275nm. The spacing of atoms within the box-shaped silicon crystals is used like hash marks on a ruler to measure the dimensions of these test structures. Industry can use these reference materials to calibrate tools to reliably measure microprocessor-device gates, for example, which control the flow of electrical charges in chips.

“We have caught up to the semiconductor industry roadmap for linewidth reference-material dimensions with this work,” says Richard Allen, one of the NIST researchers involved in the project. “With the semiconductor industry, one has to run at full speed just to keep up.”

The new reference materials, configured as a 9mm x 11mm chip embedded in a silicon wafer, are now being evaluated by SEMATECH member companies. Compared to a batch of prototype test structures produced by NIST in 2001, the new reference materials offer a wider range of reference feature sizes, including some that are much narrower, and they are measured much more precisely (with uncertainties of <2nm compared to 14 nm previously). In the absence of reference materials such as these, companies have calibrated measurement tools using in-house standards, which may neither be accurate nor agree with each other.

The program was a collaboration between NIST, SEMATECH, VLSI Standards Inc., and Accurel Systems International Corp. NIST researchers handled the layout, etching, AFM imaging, and lattice plane counting tasks; a key step in the patterning of the silicon lines in the test structures was performed by VLSI Standards; the SEM imaging was performed by SEMATECH and NIST; and the HRTEM imaging was performed by Accurel Systems.


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