A panel on strain engineering at the recent IEDM conference featured experts in favor of different approaches. The two take-aways representing the consensus, according to panel moderator Professor Scott Thompson of the U. of Florida, were that strain engineering is real, and that IC manufacturers should use all improvements possible using strain as long as they are additive.
“There was complete agreement among panelists that strain is the technology that extends Moore’s Law for at least three more generations and perhaps even down to the 32nm node,” explained Thompson. “If you look at improving device performance, strain can potentially improve performance 3x in PMOS – a phenomenal improvement compared to other methods such as FD-SOI, metal gate/high-k, FinFET or tri-gate.”
After agreement on general principles, however, the panelists diverged as to whether only uniaxial local strain, global biaxial strain, or some combination would be better. SiGen CEO Francois Henley favors the combination approach of global uniaxial strain, while IDMs such as Intel, TI, and TSMC are in production with devices that incorporate uniaxial local strain. Henley asserted that global uniaxial strain is the way to go, contending that a low energy approach to strain engineering is needed. MIT professor Judy Hoyt disagreed, saying that she thinks the jury is still out on that issue.
With the focus placed squarely on yield concerns, WaferNews asked Thompson to explain the concept of low energy and strain engineering. “The higher the ‘energy,’ or the higher the stress, the more likely the lattice will relax and form a dislocation,” said Thompson. “The formation of dislocations at high stress will eventually limit how far strain can be extended, so it is highly desirable to use a stress technique that enhances mobility at low strain.” To date, both local and global uniaxial strain are able to accomplish this for p-channel devices, he noted. “For n-channel devices, more options exist since both uniaxial (local and global) and biaxial stress offer high mobility enhancement at low strain.”
The topic of using SiGe in the channel also was discussed, and again there was only some agreement among panelists. For PFETs, Hoyt believes that there will be a topping out in terms of the channel performance that can be attained with strain, and therefore, the composition of the channel will need to be changed. She thinks that material will be SiGe. Ken Rim of IBM spoke cautiously about the problem of controlling dislocations when using SiGe in the channel, yet he noted that eventually, there might be a need to use SiGe.
An additive approach to strain engineering strategy
The IEDM strain engineering panel session provided a platform for the session’s sponsor, Applied Materials, to describe its mobility scaling strategy (vs. geometry scaling). Farhad Moghadam, SVP of the company’s thin films product business group, said its approach is to offer six different films – tensile (NMOS)/compressive (PMOS) silicon nitride, tensile HARP PMD and STI, selective epi SiGe, and biaxially strained SiGe substrates–that could be used in a “pick and choose” manner dictated by specific applications and device performance requirements. All six films could even be used in the same device depending upon the performance and application requirements.
Using this approach, end users can differentiate their devices by the process and architecture they choose, in addition to design and layout. “These films are all additive steps with respect to [improving] drive current,” said Moghadam. He believes that more of these films will need to be implemented simultaneously as the industry moves from 65nm to 45nm, and on to the 32nm node.
A key enabler of any of the six film types is surface preparation, which ensures integrity of the interface–important for subsequent depositions. Controlling plasma bombardment and the cathode to anode ratio are also vital along with the usual parameters of temperature, pressure and reactor design. “Film stoichiometry and composition are maintained by controlling the reaction times as well as the switching in/out of precursors in the reaction chamber,” Moghadam told WaferNews. “For selective SiGe recessed source/drain applications, the recess geometry, recess etch characteristics, surface preparation, SiGe epitaxy process, and composition control are critical to optimizing the local strain in the channel.” – Debra Vogler