SEMATECH Pinpoints 2006’s Biggest Technical Challenges

(April 21, 2005) Austin, Texas &#8212 SEMATECH announces and identifies its Top Technical Challenges for 2006, continuing to underscore advanced gate stack, 193-nm immersion and EUV lithography, mask infrastructure, and low-k dielectrics with process compatibility. For the first time, consortium leaders also placed planar bulk transistor scaling on the list. The Top Challenges are used to focus SEMATECH’s resources on the most critical of approximately 75 projects that it maintains in key areas of semiconductor and related R&D. The research portfolio is developed by the consortium’s Executive Steering Council (ESC), in consultation with corporate managers.

(April 21, 2005) San Jose, Calif. &#8212 North American-based manufacturers of semiconductor equipment posted $1.02 billion in orders in March 2005 (on a 3-month average basis) and a book-to-bill ratio of 0.81, according to SEMI’s March 2005 Book-to-Bill Report.


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