3-D Integration of ICs



Microelectronic applications tend toward more complex components with higher integration at the chip level, higher frequencies, more functionality, and increased performance. Miniaturization of all mobile communication applications demand smaller, less expensive packages and improved time to market – all at continually lower costs. In a growing number of consumer applications, miniaturization includes the combination of electronic circuits with sensor elements based on MEMS technology. These hybrid packages face additional challenges: hermetic requirements, interacting with an environmental property they must measure, and minimization of mechanical stress.

Several approaches in the semiconductor industry are pushing to meet the requirements of the latest product applications including both package- and chip-level integration. Packages are piled up, bare die are stacked within a single package, chips are 3-D vertically integrated, and integration also takes place on the chip itself using embedded technologies to create a system-on-chip (SoC).

In high-performance, low-cost solutions, 3-D system integration is the ultimate step toward integration using individually processed components of otherwise incompatible technologies. 3-D vertical integration comprises IC functionality as well as hybrid integration of IC and MEMS functionality. In 3-D integrated systems, the peripheral electrical interconnections between die are replaced by vertical signal lines directly connecting corresponding circuit blocks – like global on-chip wiring of planar SoC die. The key to 3-D system integration is an interface between the top and bottom chip that allows the highest interconnectivity and shorter interconnects, resulting in reduced interconnect delay, power consumption, resistance, and capacitance.

Figure 1. Principle chip-to-wafer process flow.
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There are a number of approaches under development that target the high interconnectivity interface challenge. Some of them allow the combination of just two die in face-to-face orientation, while others use modular approaches for more than two chips stacked on each other. With modular approaches, the electrical interconnect typically is created using wafer through-hole technology to connect the pads of the top chip through the silicon substrate to the bottom one.

In addition to IC packaging requirements, successful hybrid integration of ICs and MEMS requires additional functionalities, such as encapsulation in hermetic cavities. The hermetic cavity package encapsulates the fragile parts of MEMS devices, such as the freely moving structures in MEMS accelerometers for automotive airbag systems. These structures must be protected against particles, moisture, and mechanical stress. The cavity environment also affects the performance of the device, so hermetic and ambient characteristics must be controlled to optimize the device characteristics.

Wafer vs. Chip Bonding

Manufacturing of 3-D integrated and 3-D hybrid packages can be based on wafer-to-wafer or chip-to-wafer bonding techniques. Wafer-to-wafer bonding equipment is commonly used, thanks to its intensive use in MEMS packaging, but the approach has inherent limitations that are especially significant for 3-D integration of costly ICs.

To overcome the limitations of wafer-to-wafer bonding approaches, chip-to-wafer bonding is an alternative that allows the flexible combination of different technologies, materials, and geometries. Concerns about chip-to-wafer bonding, however, include limited throughput caused by sequential bonding of individual die, and the ability to allow evacuation or control of the environment (and thus, the cavity environment in MEMS capping processes).

A wafer-level technology* that enables manufacturing of 3-D integrated assemblies has been developed. The technology takes advantage of synergies between MEMS and IC packaging equipment to overcome challenges and allow high-throughput processing and the proper environment control.

The basic idea behind the new technology is to split the complete process into two parts – an alignment and pre-bonding process that defines the accuracy of the assembly and a permanent bonding process that forms the final interconnect. Permanent bonding typically is achieved by introducing temperature to the interconnect layer while maintaining force on the chip’s backside.

Figure 2. High-speed flip chip equipment used for pre-bonding top chips to the bottom wafer.
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Decoupling of alignment and permanent bonding offers significant advantages in the production of chip-to-wafer assemblies. High-throughput alignment can be performed at room temperature without the disturbing influence of process temperature and high force on placement accuracy. In addition, existing and mature die bonding equipment can be used instead of highly customized tools necessary for in situ processing. Permanent bonding is achieved in a second process step with a fully assembled bottom wafer. Through this batch fabrication, the time-consuming interconnect formation is done for all devices on one wafer, in parallel. Throughput normally is defined by the speed of the die bonder, therefore low-cost, high-volume production can be achieved. A new bonder** allows for careful control of processing parameters in terms of temperature, force, and ambient gas. The bonder is in a vacuum chamber, which allows for evacuation and controlled ambient gas. A homogenous force can be applied to every chip, even those with different heights.

The key to separating the alignment and bonding steps is an effective tacking method to fix the die temporarily and allow safe transfer from the die to a chip-to-wafer bonder, without the need for dedicated clamping fixtures. Depending on the material composition of the opposite contact surfaces and the final application of the assembly, a number of tacking methods can be used.

The new technology enables interconnect processes on the component level, ranging from adhesive bonding and soldering to interconnect methods previously restricted to wafer-to-wafer bonding approaches such as anodic bonding, fusion bonding, or glass fritt.

Future Application Range

The future application range includes multi-level stacked packages, flip chip connection of electronics to MEMS devices, chip-level packaging of MEMS devices, and hermetically sealed packages for MEMS devices.

Multi-level Stacked Packages. Some investigation has been carried out into the stacking of multiple chips for even denser integration of devices. This stacking technology may also be used for integration of MEMS devices with electronics, for example, where some of the layers could be MEMS devices rather than microelectronic chips.

Flip Chip Connection of Electronics to MEMS Devices. The fact that flip chip technology can be used to integrate MEMS devices with electronics is well known. Both the MEMS device and the electronics device can be placed onto a substrate or, alternatively, the MEMS device can often be used as a substrate. The latter method means that handling of the MEMS device is not such an issue. Many devices are fragile, and this approach means that the device does not have to be picked up and placed.

The combination of the new technology described in this article with the production of chip stacks using a process*** developed by Infineon and Fraunhofer Institute offers several advantages over current technologies:

  • The resistivity of Cu3Sn is lower than that of conventional solder (8.9 µΩ-cm, as opposed to ~16.5 µΩ-cm for Sn-Pb solder);
  • The flipped chip is much closer to the substrate than it would be with a conventional flip chip process (15 µm, as opposed to ~300 µm).

These advantages mean that a better quality electrical connection can be achieved by using the process. For many applications, this could be a key advantage. The I/O signals of MEMS devices are often small and vulnerable to noise. For such devices, the quality of the electrical connection is important.

Chip-level Packaging of MEMS Devices. Many MEMS devices are more fragile than solid-state electronic devices, normal packaging processes are not always possible. By using an intermediate packaging stage (chip-level packaging), such devices can be made robust enough to be put through a standard packaging process.

Figure 3. This chip-to-wafer bonder enables bonding of as many as 8,500 chips/hr.
Click here to enlarge image

The intermediate packaging stage uses a cap to protect the fragile microsystem. For cleanliness reasons, the cap is often applied before the wafer is diced. This provides protection from sawing debris. When the wafer is diced, the cap means that a standard vacuum tool can pick up devices.

Hermetically Sealed Packages for MEMS Devices. Many sensors and actuators require a vacuum package. The new technology could be used to create vacuum packages for such devices at the chip level. Similarly, sealed vessels could be created for microfluidic devices at the chip level. The main advantages include:

  • The material can be used to create seals between a wide range of materials, such as silicon, quartz, ceramics, etc.
  • In contrast to many technologies, automated wafer-level packaging is possible without the requirement of wafers being the same size. By using pick-and-place technology, packages can be built up using small, separate components. An example is a customer requirement for a vacuum package to be created by placing small rings of piezoelectric material in conjunction with molybdenum caps onto a silicon wafer to form a chip-level vacuum package.


A production technology has been developed to enable 3-D vertical integration of ICs and hybrid integration of MEMS and ICs based on a broad range of different interconnect methods.

*Datacon’s Advanced chip-to-wafer technology.
**Datacon’s Chip-to-wafer bonder.
***SOLID Face-to-face.

CHRISTOPH SCHEIRING, manager of Advanced Technologies, and HANNES KOSTNER, Technology Development engineer, may be contacted at Datacon Technology AG, Innstraße 16, A-6240 Radfeld, Tirol, Austria; 43-53 37-6 00-0; e-mail: [email protected]. PAUL LINDNER, CTO, and STEFAN PARGFRIEDER, Product manager, may be contacted at EV Group, DI Erich Thallner Straße 1, A-4780, Schärding, Austria; 43-77 12-53 11-0; e-mail: [email protected].


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