Mass Imaging Responds to Wafer-Scale Packaging Advances



Semiconductor vendors are excited by advanced packages such as flip chip, several variants of chip-scale package, and system-in-package (SiP). Packaging overheads are low, leading to highly miniaturized components, and electrical performance is enhanced. These are ideal attributes for broadband applications like IP-based voice and data communications, Gigabit and 10G Ethernet, and 3G mobile. SiP, however, offers a potentially more flexible, lower-cost alternative to the system-on-chip (SoC). It is more tolerant of redesign and inherently able to support mixed technologies.

Component assemblers need improved package assembly processes and techniques to create large area arrays, which can feature several hundred interconnects. The objectives are greater throughput, higher end of the line yield, and lower capital expenditure and cost of ownership to minimize the cost per package.

One company* has addressed these challenges with a wafer bumping solution that is capable of creating interconnects on a pitch as fine as 200 µm. The process is more tolerant of ambient conditions, occupies less factory space, consumes less energy, and generates less waste.

High-accuracy mass imaging must now prove that it can keep pace with future packaging advances. While new generations of chip-scale packages are targeted at bump pitches significantly below 200 µm, and even below 150 µm, the established stencil design rules are already stretched. In addition, several territories are about to launch initiatives to eliminate lead from electronic products – either compulsorily or voluntarily. Some process issues have already been discovered when screen printing with lead-free pastes at normal surface mount technology resolutions, but so far little is known about how these issues will manifest themselves or be overcome at the wafer level.

High-speed at Wafer Level

High-accuracy mass imaging for wafer-level applications exploits recent advances in screen printing for surface mount technology pre-placement to create large numbers of area array interconnects at high speed. There are three key enablers: enclosed print heads technology has achieved paste volume repeatability well beyond the requirements of ordinary surface mount technology, into wafer-level territory; precision manufacturing of electro-formed stencils, with high dimensional stability and excellent paste release characteristics; and motion controls based on linear motor technology, with new position encoders that enable high repeatability at wafer-level resolution.

New technologies, in addition to automated handling systems, have emerged. These include paperless cleaning systems suitable for cleanroom conditions and new evolutions of the fully enclosed print head. The low waste achieved by these systems is particularly important when using specialized, expensive, low-alpha solder pastes for ultra-fine pitch bumping.

Wafer bumping by high-accuracy mass imaging does require the use of design guidelines tailored for each application (Figure 1). In addition, specific equipment, materials, and process instructions must be followed to establish a robust, high-yield wafer bumping print and reflow procedure.

Figure 1. Handling for carriers and wafer sizes up to 300 mm enables an in-line solution.
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In the imaging step, an over-printing strategy is used to achieve bump height targets of 80 to 150 µm on pitches of 150 to 500 µm (Figure 2). This technique requires rigorous application of design rules when creating the stencil. It also is necessary to pay careful attention to the design of bond pads, allowing sufficient contact area to achieve sufficient solder joint strength for a given standoff.

Figure 2. Over printing to achieve specified bump height using high-accuracy mass imaging.
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Solder bump sizes are affected by the shape of the wettable bonding area of the chip pads. This shape is not necessarily dependent on the geometry of the pads, but is chiefly determined by the passivation opening overlying the pads.

Figure 3. Paste is deposited through apertures typically 0.003 in. deep.
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In a typical example, solder paste is deposited through apertures measuring 6 x 19 mils high and 6 mils in diameter (Figure 3). This process is generally suitable for bumping pitches for bumping pitches down to 200 µm for full array die, and 150 µm for peripheral array designs.

Meeting Emerging Challenges

As bump pitches shrink, the volume of each solder bump will also shrink. Paste volume repeatability becomes more important if coplanarity is to be maintained. There are two aspects to achieve high paste volume repeatability: 100% aperture filling, and optimal paste release.

A new technique is emerging to enhance paste release for wafer-level applications. When screen printing with a traditional emulsion screen and squeegee, the stencil tends to peel away from the substrate surface, resulting in a progressive reduction of adhesion between the paste and the stencil until the stencil separates fully from the substrate. This has a beneficial effect on paste transfer efficiency and repeatability. But the majority of today’s mass imaging processes – including semiconductor assembly processes – feature a metal stencil, such as a laser-cut stencil. This is brought into direct contact with the substrate before the squeegee or enclosed head begins its excursion. Afterward, the substrate is moved directly downward away from the stencil. The combination of forces that result in the peeling action are replaced by a vertical pulling force.

By investigating the movement of metal stencils during separation, the separation begins at each outside edge of the stencil and converges toward its center. The center is the last part of the stencil to release. This separation also accelerates toward the center of the stencil, which does not make for consistent paste release.

Figure 4. Creating a peeling effect at separation maximizes paste release.
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Regaining the peeling action displayed when a conventional emulsion screen separates is crucial to developing a repeatable process for bump pitches of 150 µm and below (Figure 4). To achieve this, an optimized stencil tensioning mechanism combined with a different separation action was developed. The frame is capable of automatically adjusting the tension within the foil to optimize both the deposition and separation phases of the process. The tension is adjusted pneumatically, using the standard air supply available on any automated mass imaging platform.

Lead-free Bumping

Wafer bumping must also respond to the industry-wide transition to lead-free solder alloys. Pastes manufactured with these alloys are known to display a different rheology than lead-containing predecessors. Surface mount technology assemblers are now finding that they must subtly alter their screen printing parameters to optimize processes for lead-free printing. The same is true at the wafer level, where the higher viscosity and greater mental content of the new pastes will have implications for aperture filling, paste on pad, and shrinkage during reflow. Responses will likely come in the form of revised design rules for pads and apertures. Research into lead-free screen printing for surface mount technology applications has shown the process is now sensitive to stencil separation speed. This adds an extra dimension when calculating the process window. Research into separation speed, as well as putting the peel back into the separation action are important avenues for lead-free wafer bumping research.

The high metal content of lead-free pastes implies lower shrinkage during reflow. As a result, there will be a closer relationship between bump height and standoff height. Process developers need to fully understand these relationships to determine the paste volume required to achieve a target bump height, and design pads and corresponding stencil apertures accordingly. Pad design will also affect solder joint reliability, since this is a function of standoff height.

Lead-free pastes have lower wetting forces and show less inclination to “pull” the solder onto the pad in the event of a small mis-registration: stencil-to-wafer alignment, as well as stencil quality and fidelity for high paste on pad repeatability, will be critical in lead-free wafer-level applications.


High-accuracy mass imaging is bringing speed and cost advantages of stencil printing principles to advanced packaging assembly applications. But the demands are continually changing, calling for more I/Os and progressively smaller interconnect pitch, as well as the challenges of lead-free assembly. Further R&D, as well as adoption of new techniques already in the pipeline aimed at increasing repeatability for low-volume deposits, will enable next-generation packages at commercial volumes and prices.

*DEK International.

RICHARD HEIMSCH, president, may be contacted at DEK International, Geroldstraße 28, 4 Stock, Ch-8005, Zurich, Switzerland; 41 1274 8025; e-mail: [email protected].


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