By J. Robert Lineback
Can SEMATECH Inc. help find new ways to squeeze more life out of conventional planar bulk transistors while delaying the need for nonclassical CMOS devices, such as FinFETs or other multigate FETs? That’s the newest objective being added to SEMATECH’s list of top 10 technical challenges for 2006, which will be used to formulate and focus about 75 R&D programs next year.
Inclusion of planar bulk transistor scaling in the top technical challenges reflects growing interest among the consortium’s member companies to extend what they’re doing now into the 45nm and possibly 32nm process nodes, explained SEMATECH president and CEO Michael Polcari. “The longer we can extend the present technology, the more cost-effective it usually is,” he said, adding that many of SEMATECH’s programs have been aimed at “pushing the limits back” vs. launching totally new technologies.
Similar to SEMATECH’s 2005 list of top technical challenges (see WaferNews V11n25, June 12, 2004), the new set of priorities for R&D programs covers a range of issues in 193nm immersion lithography, photomask infrastructure, photoresist, extreme ultraviolet (EUV) exposure technologies, advanced gate stack concepts, nonclassical CMOS transistors, low-k dielectrics, metrology, and wafer fab productivity. Missing from the 2006 list released on April 19 is 3D interconnect technology, which was launched by the Austin, TX-based consortium a year ago to help develop an alternative to simply shrinking and packing more devices on a single CMOS die. Polcari told WaferNews that the 3D interconnect program continues, but it was simply bumped off the top technical challenges list when bulk planar transistor scaling was added for the first time.
While SEMATECH’s work on revolutionary technologies continues in nonclassical CMOS transistors, EUV lithography, and advanced gate stacks, the elevation of planar transistor scaling to the top of the technical challenges list reflects new realities in today’s semiconductor industry, which is feeling more pressure to find cost-effective approaches to manufacturing next-generation products during the next five years. Greater emphasis is now being placed on “what are the right lists of projects that could make an impact on the ability of members to extend the planar transistor maybe one more generation than they thought was possible,” Polcari explained. “That would be a tremendous cost advantage” for SEMATECH shareholders AMD, Hewlett-Packard, IBM, Infineon, Intel, Freescale (formerly Motorola’s semiconductor group), Philips, Texas Instruments, and Taiwan Semiconductor Manufacturing Co. (TSMC), as well as other companies involved in the International SEMATECH Manufacturing Initiative (ISMI) subsidiary, he said.
Industry observers believe SEMATECH’s increased focus on CMOS planar transistor scaling makes sense. “A lot of this is a result of what has happened over the last four years — in particular the progress made in substrate engineering and the introduction of strained silicon as well as SOI [silicon-on-insulator wafers],” observed Dean Freeman, principal analyst in Gartner Inc.’s Dataquest semiconductor manufacturing research group in San Jose, CA. “With these engineered substrates they can get a couple more generations out of planar transistors without having to go to high-k [dielectrics in (US$3.9 million) worth of shares gate stacks to reduce leakage at 45nm and 32nm nodes]. That’s good news. My guess is that SEMATECH is being asked to do more with the ‘low-hanging fruit’ using SOI and strained silicon,” Freeman told WaferNews.
The Gartner Dataquest analyst also believes industry efforts in FinFETs and multigate transistors will not be ready for 45nm processing “and you could argue they won’t be ready for 32nm as well,” Freeman said. “But my guess is that if they can extend the planar transistor to 15nm, they will jump at it because the industry is very conservative and device makers want to stick to what they know.”
The industry’s conservative approach to R&D also is driving greater collaboration in breakthrough technologies that eventually will be required to continue the pace of Moore’s Law for device shrinks and transistor integration. In immersion lithography, SEMATECH is shifting more of its attention to next-generation high-index fluids and low-k1 processing with high-NA lenses, now that the early tools are moving to the prototyping phase in fabs. SEMATECH’s Advanced Gate Stack program is focused on creating reliable transistor technology using high-k dielectrics, and dual-workfunction metal gate transistor processes for n– and p-type devices used to build CMOS integrated circuits. “Everyone believes that we are going to insert high-k and metal gates at some point. It’s just a question of when,” Polcari said. In the interconnect area, SEMATECH engineers are now evaluating two leading low-k dielectric candidates for 45nm processes and the potential for k-effectiveness down to 2.5.
When asked to describe the leading low-k materials, Polcari chuckled and wouldn’t disclose any details about the porous films or processes. “We have to save something for the paying members,” he added. — J.R.L.