SEMATECH & Novellus to host workshop on copper resistivity in advanced ICs

AUSTIN, TX and SAN JOSE, CA — (MARKET WIRE) — 04/28/2005 — SEMATECH and Novellus Systems, Inc. will co-host a critical industry meeting, focusing on ways to extend the use of copper in advanced semiconductors, on June 9 at the Hyatt Regency San Francisco Airport Hotel in Burlingame, CA.

The Copper Resistivity Workshop, held in conjunction with the International Interconnect Technology Conference (IITC), will address challenges facing interconnect technologists at the 45 nm technology node and beyond. In particular, engineers will seek approaches to dealing with increasing copper resistivity as physical linewidths shrink below 90 nm. Sessions will include:

— Consensus-building on the contributions and root causes of metal line
resistivity increases at wire widths below 90 nm
— Discussion of the performance and reliability impact of line
resistivity increases
— Dialogue on potential solutions to alleviate resistance increase from
the perspectives of materials, process and integration, and circuit design

Subject-matter experts at the workshop will include Azad Naeemi of Georgia Tech; T.S. Kuan of the University at Albany; Sywert Brongersma from IMEC; and Guenther Schindler of Infineon and N. S. Nagaraj of Texas Instruments. Registration is free for employees of Novellus and SEMATECH member companies, and for technical journalists.

Interested persons are invited to contact [email protected] to register, or to visit for more information.


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