Software addresses nanoscale chip’s performance

May 19, 2005 — Golden Gate Technology Inc. of San Jose, Calif., unveiled two software products that it said reduced power consumption in chips and allowed for sophisticated on-chip power management.

Wires account for 5 times more power consumption than transistors at the 90-nanometer node, and 30 times more power consumption than transistors at 35 nanometers. Since wires burn most of the power on nanometer chips, Golden Gate said its power reduction software gives wires the first priority with a patent-pending optimization technology called, WiresFirst. Its Power Optimize Gold reduces power at many stages in the physical design flow.


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